I don't see why, I will consider a big fail if the theoretical peak per core is unchanged in Skylake vs. Haswell, they can't pull the FMA trick another time as you said
Like I said before, better power efficiency can also be traded for better performance. Note for instance that the
Sandy Bridge-E disables two cores so it doesn't exceed the TDP target. By saving 25% of power per core it would have been able to enable those cores and achieve 33% higher performance (assuming good yield). Alternatively they could clock things higher, or do a bit of both.
You need to realize that at 14 nm and below, transistors will be incredibly cheap, so adding more cores isn't much of a problem. The real problem is the increase in power consumption this would bring. So anything that improves the clock gating opportunities is a very attractive proposition.
Also, while AVX-1024 executed on 256-bit units indeed wouldn't increase peak performance per core per clock, in reality that peak performance is hardly ever reached. At least part of that is to blame on cache misses and imperfect scheduling, and AVX-1024 does help with that so it achieves higher
effective performance per core per clock.
if 22nm MIC can have 64x full width 512-bit units, I don't really see why a (16 cores) 14nm Skylake can't have 32x full width 512-bit units (2 units per core)
The MIC is an in-order architecture at a relatively low clock frequency. And it has just one 512-bit unit per core, while you're asking for two per core on a much more complex out-of-order architecture at a higher clock frequency. And since Sandy Bridge actually has three 256-bit units it can be argued that any 512-bit design would also need three units, not two, to avoid reducing the performance for legacy workloads. And you also need twice the bandwidth per core compared to the MIC.
The ALUs themselves are really quite small, so that's not the problem. The real problem is getting data in and out of them while still meeting timing constraints. And with a superscalar out-of-order architecture at high frequency that's a whole lot harder. Even at 14 nm it just isn't realistic to expect 512-bit units.
If you want higher throughput, just add more cores. Sandy Bridge-E has 8 cores at 32 nm, so at 14 nm they could pack 32 cores into the same area. But like I said above, you need AVX-1024 executed in four cycles to keep the power consumption acceptable.
I'm not against this since I see AVX-512 as the most likely next step, I just find rather unlikely to see AVX-1024 introduced at the same time than AVX-512, and I can't really imagine AVX-512 being introduced without increasing the peak throughput
I hope that by now it has become clear that peak throughput per core per clock doesn't determine total effective throughput. You have to take into account how many cores can be used, what their switching activity will be like, and how efficient they will be. If you look at the big picture, AVX-1024 executed on 256-bit units is far more likely to be implemented long before they'd consider adding 512-bit units.
One last thing to keep in mind is that Intel is going to use the same core architecture for everything ranging from Xeons in supercomputers to low-power chips for ultrabooks. In particular the latter would make having 512-bit units impossible to justify, while the Xeons can simply have lots and lots of cores.
Facebook
Twitter