- Apr 22, 2012
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I am not seeing the new SATA Express though.
DDR4 is the only interesting thing here.
highest clocked memory at 2133...
Not that I will ever use that much RAM, but why the restriction of 1 DIMM per channel?
Is this something peculiar to DDR4 (cannot be....otherwise how will they handle the requirements of datacenter consumers when Haswell-E based Xeons are released) or an effort to restrict the amount of system RAM so that Haswell-E does not eat into the IVB-E based Xeons?
If only one DIMM module can be connected to one channel, this will become a problem for some server users (VPS etc). They like to populate all 8 slots with current gen SB-E Xeons.
Of course, we do not know the capacity of a single DDDR4 DIMM stick. 32 GB might be commonly available by the time Xeons based on Haswell-E launch. Meh, should be okay for most users. There's always dual-socket for those who need greater density.
"DDR4 also anticipates a change in topology.[disputed discuss] It discards the multi-drop bus approach used in previous generations in favor of point-to-point where each channel in the memory controller is connected to a single module.[6][9] This mirrors the trend also seen in the earlier transition from PCI to PCI Express, where parallelism was moved from the interface to the controller,[9] and is likely to simplify timing in modern high-speed data buses.[9] Switched memory banks are also an anticipated option for servers.[6][9]"
http://en.wikipedia.org/wiki/DDR4_SDRAM#Technical_description
does that mean that for a mobo to sport 4 dimms it has to be quad channel ??
We have heard early reports of 8 core chips before but they always seem to get phased out as the release nears. Hopefully this one will stick. I have been holding off on upgrading until I could double my cores and likely OC to 5Ghz. Looks like just one more year of waiting!
Sounds possible, depending on how the mem controller is setup and if a switch is/isn't used.
Maybe having the possibility of adding 1, 2, 3, or 4 each potentially increasing bandwidth
The need for pairs will be removed.
I get the sense that 2 dimm boards could become more common if they can increase the density a lot with this tsv stuff.
Looks quite nice actually!
I have some questions though:
-Approximately how much is an 8 core Haswell-E likely going to cost?
-How come the DDR4 interface is limited to 2133 MHz? Would it be that hard to increase the bandwidth further? I know it will be point to point so if several memory slots are used that will help, but still.
-Looking at the roadmap I do not see 14 nm mentioned at all, despite that it stretches to Q1/Q2 2015! How should we interpret that? Is 14 nm delayed, or will Intel use those fabs for the mobile CPUs competing with ARM?
-No Broadwell on the Desktop roadmap. What's up with that? Will it be mobile only after all?
8 cores will most likely cost the same as 3930K and 3970X today.
14nm is on track. But why would you talk about 14nm on an enthutiast roadmap that will use 22nm for its CPUs.
The problem is Skylake will be out H1 2015.