cytg111
Lifer
- Mar 17, 2008
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Put me under "I disagree". Just how AVX2 only benefits certain types of computation benchmarks, there are other architectural features that can skyrocket other types of traces. And it can be done without additional instructions or additional ALUs. On top of that, remember instruction level is just one level of abstraction. Consider the uop flows for complex instructions that can be improved. Same instruction... just faster.
I have never run SPECfp but I do know it composes of many FP intensive traces and I guess the final score is a big average. Has anyone attempted to see the speedup of the individual traces? You might be surprised.
Edit But in case anyone wanted to nitpick. Yes, SOME traces need new instructions to improve. When a certain trace is well understood and therefore very optimized for the CPU to minimize misprediction, stalls, etc.... then you start hitting the point that IPC improvements is going to require some creativity.
That might be, but evidence seems to suggest that IPC is scaling off for both Intel and AMD, converging at about the same level (yes, Intel is getting there sooner, rather than AMD-later).
