Has Intel stayed on schedule?

[Hulk]

I thought Haswell is an 8 port CPU core. That pretty dang wide. Unless you are referring to data paths or something else.

Yes the back end is now 8 ports but the front end is still the same 1 complex decoder pipe and 3 simple decoder pipes.

Perhaps the current configuration was showing just a little backlog on the back end so Intel decided to beef up the front even more (improved the branch predictor, 2x cache bandwidth, improved memory controller) and then give the back end a big boost by adding the two additional ports.

It'll be really interesting when we get Anand's review of final silicon. This is gonna sound weird but waking up to a new CPU architecture review on Anandtech has always kind of been like Christmas morning for me when I was a kid. It doesn't happen often and as a follower of the industry I really enjoy seeing how the silicon meets the pavement in the official review.

 

[Exophase]

Doesn't Poulson do something silly, like 11 or 12 width? Wonder if x86 will get that wide in the coming decade.

Poulson's front-end fetch + decode is like its predecessors. Two bundles which can each contain up to 3 instructions, so up to 6-wide. It's not comparable at all to x86 since the bundles are fixed width VLIW, which limits the decode combinations. Also worth noting that Poulson doesn't clock remotely as high as any Intel x86 CPU from the past several generations, although that's probably down to a number of reasons.

x86 has had four decoders since Core 2 first came out 7 years ago. I doubt we're going to suddenly see a huge increase in the next 10 years. Most of the instruction throughput comes from the uop cache now anyway, although that's also four wide.

 

[ShintaiDK]

Remember IA64 is not using a real time scheduler like x86. Thats one of the key reasons for the width part.

Under Core 2, Intel said the 4th issue wide gave around 5%.