Hard Core High Performance process tech - How much can frequency be increased?

[Fjodor2001]

Hi,

As you're probably aware, when designing process tech it's a trade off between transistor density and performance. Semiconductor manufacturers therefore often have one High Performance tech and another High Density tech, depending on what a certain chip benefits the most from.

So I'm just wondering how much frequency could be improved if no consideration was given to anything else, like price or transistor density (except that the CPU cores must be able to fit on the die of course).

Let's say Intel Haswell was made on such a Hard Core Performance Process (HCCP). How much higher would it be possible to clock the 4790K which today is at 4.0/4.4 GHz?

Anyone that would care to provide a rough estimate?

 

[witeken]

Let me put it this way: if all of Intel's $50B Core revenue came from i7 88W+ CPUs, and if laptops didn't exist, then you can be quite sure (I think) that your Haswell CPU would have a nice bump in frequency compared to how it is clocked today.

Not sure if that answers your question. I don't have any quantitative information, and if anyone has, they probably wouldn't share.

 

[videogames101]

Keep in mind you'd have to re-design your CPU. But, with no consideration to anything else? How about power/cooling tech? Really really fast. I think 6 or 7 GHz+, especially if you sacrifice all your yield and use only the fastest silicon. That number is mostly a guess, but if you throw out PVT pessimism (PVT optimism anyone? ) and use exotic cooling I really don't see why you wouldn't see gains like that, and I'm not even talking about process changes.

 

[ThatBuzzkiller]

There is no such thing as a trade-off between density and performance ...

Density is always dependent on transistor gate pitch size and nothing else therefore the density is always constant unless the transistor gate pitch was changed ...

Performance and lower power is the actual trade-off when moving to a smaller transistor because the chip designer has to choose whether to spend it on making it have lower voltages or increase the circuit size ...

 

[Phynaz]

There is no such thing as a trade-off between density and performance ...

Density is always dependent on transistor gate pitch size and nothing else therefore the density is always constant unless the transistor gate pitch was changed ...

Performance and lower power is the actual trade-off when moving to a smaller transistor because the chip designer has to choose whether to spend it on making it have lower voltages or increase the circuit size ...

You are mistaken, density is also dependent upon layout and other factors.

 

[Arachnotronic]

There is no such thing as a trade-off between density and performance ...

Density is always dependent on transistor gate pitch size and nothing else therefore the density is always constant unless the transistor gate pitch was changed ...

Performance and lower power is the actual trade-off when moving to a smaller transistor because the chip designer has to choose whether to spend it on making it have lower voltages or increase the circuit size ...

False. Two words "interconnect stack."

 

[Ajay]

If raw performance really mattered in terms of sales, then Intel would be delivering 20%+ increases per generation (at higher power usage). But perf/watt matters in terms of sales, so we'll never see what Intel could 'really do'.

 

[TheELF]

Google for 5ghz cpu wall

silicone can't handle more than ~5Ghz

 

[videogames101]

Google for 5ghz cpu wall

silicone can't handle more than ~5Ghz

RF CMOS circuits operate well above 10 GHz. Silicon is not the problem.

 

[jhu]

Google for 5ghz cpu wall

silicone can't handle more than ~5Ghz

Tell that to Pamela Anderson…

 

[cen1]

The fact is that transistor by it's very nature needs certain time to stabilize on either 1 or 0. So there is a physical minimum time that is needed for a transistor to switch state.

When you add line lengths, crosstalk, and other fun stuff it only goes downwards.

You can't just eliminate one factor because it's all interconnected and needs to be balanced out.

 

[ThatBuzzkiller]

You are mistaken, density is also dependent upon layout and other factors.

Layout only matters when your designing a chip, I was been specific about transistor dimensions ...

 

[ThatBuzzkiller]

False. Two words "interconnect stack."

Interconnect size =/= transistor size

 

[Ajay]

Layout only matters when your designing a chip, I was been specific about transistor dimensions ...

Which also vary within a CPU.

 

[SAAA]

Hi,

As you're probably aware, when designing process tech it's a trade off between transistor density and performance. Semiconductor manufacturers therefore often have one High Performance tech and another High Density tech, depending on what a certain chip benefits the most from.

So I'm just wondering how much frequency could be improved if no consideration was given to anything else, like price or transistor density (except that the CPU cores must be able to fit on the die of course).

Let's say Intel Haswell was made on such a Hard Core Performance Process (HCCP). How much higher would it be possible to clock the 4790K which today is at 4.0/4.4 GHz?

Anyone that would care to provide a rough estimate?

There have been many Sandy Bridges at 5+ GHz on 32nm, I don't see why Haswell or Skylake ported on that node wouldn't reach similar speeds, remember the process is also refined for years.

Plus they would have lower temperatures too because less dense means more area to dissipate heat, remove FIVR and hilariously you could probably increase speeds even more. This if power consumption and money weren't a problem of course, because dies would be larger and pricier.
Unless you remove IGP entirely too, then I can see Haswell being under ~200mm2 and TDPs in the 100-150W range.

 

[III-V]

Layout only matters when your designing a chip, I was been specific about transistor dimensions ...

Yeah, and we're talking about chips here. Your input has been entirely incorrect and irrelevant.

Hi,

As you're probably aware, when designing process tech it's a trade off between transistor density and performance. Semiconductor manufacturers therefore often have one High Performance tech and another High Density tech, depending on what a certain chip benefits the most from.

So I'm just wondering how much frequency could be improved if no consideration was given to anything else, like price or transistor density (except that the CPU cores must be able to fit on the die of course).

Let's say Intel Haswell was made on such a Hard Core Performance Process (HCCP). How much higher would it be possible to clock the 4790K which today is at 4.0/4.4 GHz?

Anyone that would care to provide a rough estimate?

There's probably not much room for growth with the materials currently being used. If you really wanted to throw cost out the window, I don't see why we couldn't have 5-6GHz CPUs right now, but of course cost is the primary motivator behind... well, everything.

So, since you can't give up on cost, you have to be able to provide improvements while standing pat or improving on cost. This essentially means new materials, and new transistor innovations (e.g. FinFETs).

The benefits brought by new channel materials like III-V and Germanium are very significant, and when we inevitably move past silicon, we'll get a good boost. If carbon nanotube interconnects come to fruition, we'll get a good boost there as well.

 

[Smoblikat]

Google for 5ghz cpu wall

silicone can't handle more than ~5Ghz

Ive run I5's at 5.4 on a hyper 212 before, so I know for a fact that your statement is wrong. Also, these arent fake boobs, we are talking about CPU's.

Silicone != Silicon

 

[njdevilsfan87]

We need a new C2D - something that will significantly lower clocks back down into the 2-3ghz yet remain just as fast or even faster than today's 4ghz+ chips.

 

[Piroko]

So I'm just wondering how much frequency could be improved if no consideration was given to anything else

As a theoretical experiment - about 100 GHz? Assuming you can come up with a design that gets by with ~5 Transistors per stage. Definitely not something as complex as Haswell though... or a Pentium 1...

Google for 5ghz cpu wall

silicone can't handle more than ~5Ghz

I'll just drop this link here. Do take note of the date.

 

[jhu]

We need a new C2D - something that will significantly lower clocks back down into the 2-3ghz yet remain just as fast or even faster than today's 4ghz+ chips.

So, what you really want is Intel to make a really low IPC processor, clock it really high, sell that for a few years as the "mainstream CPU", then return to Skylake lineage just so we have the illusion of significantly increased IPC? Because that's exactly what happened last time.

 

[schmuckley]

Google for 5ghz cpu wall

silicon can't handle more than ~5Ghz

ftfy..Oh no?

Tell that to Pamela Anderson…

LOL

 

[soccerballtux]

it's like 100 or 200 ghz or something with germanium. 2 orders of magnitude.

Intel is working on using it. meeting resistance. sorry I'm so general I have trouble remembering source details.

 

[ThatBuzzkiller]

Yeah, and we're talking about chips here. Your input has been entirely incorrect and irrelevant.

Assert whatever you want ...

Nothing will change the fact that transistor density is solely dependent on the transistor dimensions ...

 

[Ken g6]

it's like 100 or 200 ghz or something with germanium. 2 orders of magnitude.

Intel is working on using it. meeting resistance. sorry I'm so general I have trouble remembering source details.

Is that another way of saying they're running into heat issues? :sneaky:

 

[Ajay]

Assert whatever you want ...

Nothing will change the fact that transistor density is solely dependent on the transistor dimensions ...

How many times do you need to be told that that isn't true before you will understand??? There are actual design rules that limit the maximum xtor density. It's limited in the PDK and hence, the actual CPU/SoC design.