Hammer = the end of the overclock?

[KenAF]

With Hammer, there are no accessible bridges. With Hammer and its Hypertransport, everything is is point to point/switched. There is no system bus to overclock. There is no "FSB" to increase from 133 to 166, or 166 to 200.

For those that don't recall, the memory controller is integrated on the Hammer processor die, and it eliminates the traditional system bus; this feature should substantially reduce memory latency. The integrated memory controller on Clawhammer is 64-bit (single channel DDR), and will run at 133MHz or 166MHz, but again, there is no system bus to change or configure through the bios. There is no way to change memory timings, since these are predefined in the processor's core logic.

If it is impossible to overclock Hammer...how will that impact its adoption in the enthusiast scene?

 

[XFreebie]

its hammer time!

 

[XFreebie]

im sure there will be a way, for example my abit kt133 motherboard lets me do that incremental thing that's independant of the fsb

 

[jpprod]

While Hammer won't have a FSB in the traditional sense, not being an asynchronous piece of silicon, it still needs a system clock. And this is most definitely provided by a clock generator on the motherboard. That naturally means that overclocking is possible 😉

 

[andreasl]

While the Hammer will have a system clock it's quite likely that this clock will also drive the support chipsets, for cost reasons. So it will probably be possible to overclock the CPU (depending if the motherboard supports it) but it may still result in overclocking the other components as well. We'll just have to wait and see how they have designed this.

 

[Lithium381]

I don't really see the real NEED to overclock that much, it used to be awsome when you could get another 20% out of your CPU...but now you'll get a 50mhz bump out of 2000....it's not that much of an increase to risk unstability, but i understand that it's an addiction....i've tried it once or twice...to each his own though.

 

[zodder]

I love the old days of the 700e p3s (Cb0) that could hit a gig, np. That has to be one of the all-time greatest overclocks. 🙂

 

[ElFenix]

might have a fixed ratio of the FSB analog to the memory bus.

 

[THUGSROOK]

AMDs can overclock??? 😉

 

[sandorski]

We'll have to wait and see I suppose. I've done some overclocking before with a couple k6-2s and my Duron, but I found that my 1.2 Tbird and XP 1700+ was plenty fast and chose to leave both at default speeds.

 

[AthlonRaider]

Maybe NVidia or Via will provide a solution for using faster memory than AMD intended (PC2100 & PC2700) for their Hammer series?

With Nvidia and Via releasing DDR 400 support for Athlon XP in their upcoming chipsets, maybe one can expect them to release it for Clawhammer.

But the percentage in performance gained by utilizing DDR 400 should scale much better in the Hammer setup than what would happen with Athlon XP, right? Because there would probably be no asynch FSB/Mem penalty like there is with the Athlon XP 266 with 333mhz PC2700 DDR.

 

[johncar]

Is it possible that AMD might go back to Multiplier controls on the mobo like SS7 and K6 chips?? Could we be so lucky??;-)

After all, Hammers should have to be tested for binning, which suggests "some" kind of connection on the CPU...maybe socket pins.
But AMD has always hidden those pins with an NC = No connection label. We only found the pins via tracing L1 bridges...but how to trace without bridges??? Wait and see.....
John C.

 

[TuffGuy]

<< I love the old days of the 700e p3s (Cb0) that could hit a gig, np. That has to be one of the all-time greatest overclocks. 🙂 >>


nah... my 1.0ghz MP running at 1.49ghz and 175mhz fsb is better. 😉 or my old DUAL 700e @ 1000.

 

[Athlon4all]

I wouldn't bee too sure about the fsb being gone. You still have a 800MHz HyperTransport "front side bus" to go from the CPu to the AGP Controller that will have to be controlled by the mobo.

 

[dnoyeb]

<< I wouldn't bee too sure about the fsb being gone. You still have a 800MHz HyperTransport "front side bus" to go from the CPu to the AGP Controller that will have to be controlled by the mobo. >>



I think the point is that the busses are not physically connected. Yes, you still have the PCI bus and the memory bus and the AGP bus. However, in this new configuration, the MB manufacturer can allow for seperate clock multipliers on each node if they wish.

It depends on how the chipset will handle the difference in clock speeds. If it requires communication only at multiples of the CPU clock, then we can still up the CPU clock, but only in connection with the other busses. Its a wait and see thing. There is definitely more overclockability, but that does not mean the chipset will allow us to use it.