HAMMER BENCHMARKS 800MHz!!!!! 256K L2 Cache vs Athlon MP 800!!!!

[Nemesis77]

Originally posted by: Insomniac
Doesn't it seem odd that a CPU with a longer pipeline smokes one with a shorter one at the same speed? A 40% improvement in Q3A?

No, it doesn't seem odd. You can't just assume that "Longer pipeline = worse performance", since Hammer has alot of other improvements at it's disposal. When you remember that Hammer has:

1. Integrated memory-controller. This means lower latencies and better bandwidth-utilization.

2. SSE2-support. I dunno how much Quake 3 has these optimizations though.

3. Significantly improved branch-prediction.

4. Bandwidth, bandwidth and more bandwidth! The HyperTransport-bus that connect Hammer to the rest of the system is equivalent to 800MHz traditional bus! Also, Hammer has a bit more memory-bandwidth and it can utilize it alot better than Athlon can.

5. Other miscellanious improvements. There propably are other improvements in the core. Things like wider data-bus to L2-cache (256bits vs 64bits as in Athlon).

All in all, I don't find 40% improvement in performance unreasonable.

 

[MadRat]

<<2. SSE2-support. I dunno how much Quake 3 has these optimizations though.>>

Its SSE support is improved, too. Quake!!! does use alot of SSE for its lighting effects.

 

[Insomniac]

Originally posted by: Nemesis77

Originally posted by: Insomniac
Doesn't it seem odd that a CPU with a longer pipeline smokes one with a shorter one at the same speed? A 40% improvement in Q3A?

No, it doesn't seem odd. You can't just assume that "Longer pipeline = worse performance", since Hammer has alot of other improvements at it's disposal. When you remember that Hammer has:

1. Integrated memory-controller. This means lower latencies and better bandwidth-utilization.

2. SSE2-support. I dunno how much Quake 3 has these optimizations though.

3. Significantly improved branch-prediction.

4. Bandwidth, bandwidth and more bandwidth! The HyperTransport-bus that connect Hammer to the rest of the system is equivalent to 800MHz traditional bus! Also, Hammer has a bit more memory-bandwidth and it can utilize it alot better than Athlon can.

5. Other miscellanious improvements. There propably are other improvements in the core. Things like wider data-bus to L2-cache (256bits vs 64bits as in Athlon).

All in all, I don't find 40% improvement in performance unreasonable.

I didn't assume longer pipeline = worse performance. I am saying that the IPC is lowered and I agree there are optimizations. But 40% in Q3A at 800 MHz??? That is a LOT of optimizations to the pipeline, a phenominal branch prediction unit, an extremely fast memory controller and one hell of a bus as well. (BTW--What speed is the bus?)

I am still pointing out the grayed out string in WCPUID as even more reason to doubt that review.

 

[Sunner]

Just a note on the Quake3/SSE/2 thing.

Carmack stated a long time ago that Quake3 doesn't have any special optimizations for any special instruction sets, incluidng 3DNow! and SSE, cause it simply wouldn't provide much of a boost.
According to the same .plan file, the real boost would come from the OpenGl drivers, assuming they were SSE/3DNow/Whatever optimized.

 

[XMan]

I see your point, and I agree that I am definately concerned but I think that a good sign is that TBred will be finally being launched on Monday, and not just at 2200+ but at 2GHz (2500+) and that is definately good to see considering. So, we shall see if AMD can deliver.

No 2500+.

 

[Linux23]

nice performance.

 

[staticfly]

not to mention an non-overclockable 2200+ ... they better have all those engineers working on the hammer

 

[jbond04]

Originally posted by: classy
WEll the Athlon is already leading the pack there [3D Rendering]. Let alone bringing Hammer into the picture.

At least it was...until Intel introduced the the Northwood. The Northwood brought its 3D rendering speed up to par with the Athlon, and is now surpassing it, as the P4 can ramp to higher speeds more quickly than the Athlon can.

I have a 2.53GHz Pentium 4 w/ 1GB of PC1066 RDRAM that eats a 1.5 million polygon 3ds Max scene with Global Illumination (finalRender) for breakfast. I am quite confident that it is far faster than any Athlon (even the 2200+ Tbred).

And I also don't see how the Hammer will be any faster than the Athlon at 3ds Max rendering (besides the higher clock speeds), since it will actually be a little weaker IPC-wise (longer pipeline), and the memory controller won't improve performance much, if at all (3ds Max isn't very dependent on memory speed past a certain point).

 

[Nemesis77]

Originally posted by: Insomniac
and one hell of a bus as well. (BTW--What speed is the bus?)

Hammer doesn't have traditional front-side bus, it uses HyperTransport-link to connect to the rest of the system (in multiprocessor-system, HT is also used to connect the CPU's). the HT-link that connects the CPU to the chipset has equivalent bandwidth to a 800MHz traditional FSB.

I am still pointing out the grayed out string in WCPUID as even more reason to doubt that review.

You mean the ones that would tell the multiplier, FSB and such? Well, since Hammer doesn't have traditional FSB, it's no wonder that FSB is not reported. And since the CPU-speed is determined with FSB and a multiplier, it's natural that no multiplier is reported since FSB is not reported either.

 

[MadRat]

We do know that Athlons have been cache starved since the off-die L2 cache days, so take that into account. We also know that Athlons have been kept limited to 256k L2 caches because larger caches needed a larger datapath to improve transfer rates to be any help. We also know that Athlons leak heat like a sieve, but they wouldn't if they used SOI. In effect, AMD has crept along development of the Athlon at a snail's pace for two years now with hopes and talent focused securely on Hammer:

1. The Hammer queues up twice the amount of work than the Athlon.
2. The Hammer is not bottlenecked by a 64-bit datapath to main memory and its L2 cache
3. The Hammer has a more efficient L1 and L2 cache, also better branch prediction
4. The Hammer has built-in memory controller, giving it faster memory access
5. The Hammer's caches (because the CPU uses SOI) don't leak energy as fast

We have no idea how much slack these improvements have pulled back on the aging Athlon design. We do know that the improvements were to be significant, something the article's theme seems to suggest.

 

[jbond04]

Originally posted by: BlvdKing
I have a feeling that DDR SDRAM will be a bottleneck at PC2700. That is until AMD/SiS/VIA/ALi produce a dual channel DDR SDRAM chipset for the Hammer like the one Intel is producing (Granite Bay).

It will be interesting to see how much memory bandwidth affects performance now that the CPU has an onboard memory controller running at full CPU speed.

AMD/SiS/VIA/ALi will not be introducing any dual channel DDR setup for the Hammer at all. Because the Hammer has the memory controller integrated onto the die itself, memory performance can only improve by updating the actual processor itself. So until AMD implements a dual channel DDR solution on the Clawhammer (I believe that the Sledgehammer will have one), there will never be one at all.

 

[Insomniac]

Originally posted by: Nemesis77

Originally posted by: Insomniac
and one hell of a bus as well. (BTW--What speed is the bus?)

Hammer doesn't have traditional front-side bus, it uses HyperTransport-link to connect to the rest of the system (in multiprocessor-system, HT is also used to connect the CPU's). the HT-link that connects the CPU to the chipset has equivalent bandwidth to a 800MHz traditional FSB.

I am still pointing out the grayed out string in WCPUID as even more reason to doubt that review.

You mean the ones that would tell the multiplier, FSB and such? Well, since Hammer doesn't have traditional FSB, it's no wonder that FSB is not reported. And since the CPU-speed is determined with FSB and a multiplier, it's natural that no multiplier is reported since FSB is not reported either.

I am referring to the bottom right of WCPUID. There is usually a string there like: http://www.overclockers.com/articles444/WCPUID.jpg

Instead it has been grayed out. H. Oda could use that string to verify what is displayed is accurate.

 

[staticfly]

yes that is interesting... this very well may be a fake (i hope not)... but WHY would they have grayed out the verification string? Nothing could be lost by releasing it... strange.