GPU-Z 5.8 Cool Feature-ASIC Quality

[AdamK47]

Three HD7970s. Results are consistant. Reports this every time.
1: 76.7%
2: 72.3%
3: 70.1%

I'm curious to know what the other 7xxx series cards report.

 

[badb0y]

76.7% here

 

[bryanW1995]

72.0 % on my gtx 480.

 

[VirtualLarry]

Where do you click to get it to spit out this information? I can't find it, and I downloaded the newest 5.8.

Edit: Figured it out.

I got 37.4% quality.

Edit: Gigabyte GTX460 1GB OC (715Mhz stock). Have it OCed sometimes to 820 or 840, at whatever stock voltage it comes with. (Haven't ever adjusted voltage.)

Been pretty rock-stable for me doing distributed computing.

 

[BallaTheFeared]

Grats VL, you have the worst card yet! :thumbsup:

 

[lavaheadache]

Three HD7970s. Results are consistant. Reports this every time.
1: 76.7%
2: 72.3%
3: 70.1%

I'm curious to know what the other 7xxx series cards report.

my 7970 is 65.5%


does 1125 @ stock voltage and does higher clocks with ease

 

[Tempered81]

lower% less volts to oc from what ive seen, n1 lava

 

[wahdangun]

yeah actually having hinger leaking chip is useful for overclocker hell even AMD used to sell insane high leaking chip under the name twker edition.

 

[BallaTheFeared]

They didn't sell them, they were gifted to extreme LN2 overclockers for PR

 

[njdevilsfan87]

How exactly does leaked voltage allow for better overclocking?

 

[-Slacker-]

28.9% ... is that bad or catastrophic? Or does it mean that I can now overclock the core to 5ghz or something?

edit: my vc isn't overclocked. 648mhz stock

 

[ViRGE]

How exactly does leaked voltage allow for better overclocking?

Leakage is the manifestation of overclocking headroom. It's the Pentium M principle.

Taken from AnandTech's Pentium M review:

Quite possibly the most interesting part of the way Banias was designed, relates to the processor's clock speeds and what it took to achieve them. As we've already mentioned, the CPU features a longer pipeline than the Pentium III which does help it hit higher clocks, but where does the limit exist?

In the course of designing a processor, you will eventually discover that there are certain speed paths in your CPU that will run either faster or slower than your target clock speed. If you run into paths that run slower than your target clock speed, you're in trouble, since it means that you won't be able to reach the clocks you were hoping to without some sort of a redesign. In most cases, if you find that a path is running faster than your target clock speed (e.g. finding a path capable of running at 2.4GHz on a chip with a 1.6GHz target clock speed) then you're in a very good situation, as it means that there are parts of your chip that have fairly high ceilings. For the Israel design team however, this wasn't the case.

The design team actually went in and slowed down paths that were running above Banias' target clock frequencies, because if a path is able to run faster than it should, it means that you're wasting power. The benefit of this is an even more power efficient microprocessor, but the downside is a microprocessor that has a clear clock frequency wall.

 

[-Slacker-]

So then I can overclock mine to hell right?

 

[ViRGE]

So then I can overclock mine to hell right?

Theoretically.

 

[VirtualLarry]

The design team actually went in and slowed down paths that were running above Banias' target clock frequencies, because if a path is able to run faster than it should, it means that you're wasting power. The benefit of this is an even more power efficient microprocessor, but the downside is a microprocessor that has a clear clock frequency wall.

So with Intel focusing more on power-efficiency with Ivy Bridge, does that mean that they may have intentionally slowed down critical paths, so that the CPU is more power-efficient?

That overclocking headroom may be less than SB, or non-existent?

Edit: This may indeed be the reason behind some IB leaks showing not very improved overclocking from those chips.

 

[TC777]

They have a newer version out now, with a little note below the ASIC score, basically saying that a higher percent is better.

I'm not so sure I buy that idea. How do they even know what they are calculating is even correct?

My Sapphire 7950 actually scores a little higher (76.7%) than some of the 7970 cards I have seen posted. So I doubt they are using the asic score to choose what chips go on the cards.

With no load on the card, my VDD is .803 with no load and while playing a game it goes to .943 which I don't think is wasted power like the rating claims.

 

[notty22]

Here is the new version with pic.
The description makes sense to me. Though it's hard to explain.
If you have near unlimited cooling (ln2, water) and no voltage restrictions, the leaky chip can be driven higher, more extreme.

 

[Idontcare]

Leakage is the manifestation of overclocking headroom. It's the Pentium M principle.

Taken from AnandTech's Pentium M review:

Not wanting to take anyone to task here but this is one of those "rules of thumb" that is only true some of the time for very specific reasons.

Equating leakage to clockspeed headroom is tantamount to equating a car's gas mileage to its maximum drag/transmission-limited speed.

At the device physics level there is no correlation between leakage and clockspeed. Only in practice is there sometimes a correlation that depends on a host of factors.

But not all leakage is created equal. You need leakage in a very specific part of the transistor. I can make leaky transistors by putting the contacts to close to the sidewall, or have too much punchthrough on my Halo implant, and none of that leakage is going to make your GPU clock any faster, its just going to raise the static power consumption and that's it.

Also, the text you quoted contains a logical fallacy. Clockspeed walls are not determined by the maximum clockspeed potential of the fastest circuits in the chip, they are determined by the maximum clockspeed potential of the slowest circuits in the chip.

Slowing down the already fast circuits does nothing to slow down the slow circuits, and it is the slowest of the slow circuits that determines the maximum clockspeed (the so-called "wall" in your quote) of the entire chip.

The only way you lose overclocking headroom is if they slow down the already slowest circuits in the chip, tweaking the faster ones does nothing but change the static power losses.

 

[KCfromNC]

Not wanting to take anyone to task here but this is one of those "rules of thumb" that is only true some of the time for very specific reasons.

Equating leakage to clockspeed headroom is tantamount to equating a car's gas mileage to its maximum drag/transmission-limited speed.

At the device physics level there is no correlation between leakage and clockspeed. Only in practice is there sometimes a correlation that depends on a host of factors.

But not all leakage is created equal. You need leakage in a very specific part of the transistor. I can make leaky transistors by putting the contacts to close to the sidewall, or have too much punchthrough on my Halo implant, and none of that leakage is going to make your GPU clock any faster, its just going to raise the static power consumption and that's it.

Yep. I was going to say that intentional line pushes towards power efficiency or clock speed are one thing. But it looks like this test is measuring random variation in quality from what's intended to be identical process tech for the chips. It could be that your lower "quality" chip is lucky and the random variation is going to help, but I don't see any reason why that would be more likely than the random variation hurting overclocking headroom.

 

[formulav8]

Its kinda looking like this is similar to how TCase was with A64 cpu's. People were trying to see if a lower/higher tcase value helped/hurt ocing. Likewise, ASIC is probably just a useless number kinda like tcase was for that purpose.

But it would be nice to see if there is a trend though. Lower % equal better ocing, ect.. But I doubt this ASIC number provides anything real useful outside of AMD/NVidia's original purpose...