General L1 and L2 cache questions.

[heng1028]

What is the advantages of having more L1 cache or L2 cache??

Like AMD Duron has 128kB L1 cache and 64kb L2 cache
AMD Tbird has 128kb L1 cache and 256kb L2 cache
AMD Athlon has 128kb L1 cache and 512kb L2 cache

Intel P3 Katmai has 32kb L1 cache and 512kb L2 cache
Intel P3 cumine has 32kb L1 cache and 256kb L2 cache
Intel Celeron has 32kb L1 cache and 128kb L1 cache.

For the case of Duron and celeron

Duron has more L1 cache and Celeron has more L2 cache

what are the advantges of these caches that bring performance to system??

can anyone help??

 

[Maniac9127]

<< What is the advantages of having more L1 cache or L2 cache?? >>

More data can be stored in the cache instead of the system RAM, and since the cache runs faster than the RAM, and is closer to the core, you get better performance.

 

[heng1028]

then what is the advantage of having more L1 than L2 or vice versa??
for the comparing of celeron and duron

 

[toph99]

first off, the Tbird is an Athlon. you're probably talking about the Athlon Thunderbird and Athlon 'classic'
anyways, this is how a processor works. when it's looking for an instruction, it checks the L1 first, as it is usually fastest and closest to the core. if it doesnt find what it's looking for, it suffers a miss and then checks the slightly slower L2. if it doesn't find it there, it goes to the even slower SDRAM, and if not there then the hard drive. the tbird and duron both have their l2's running full clock speed afaik, the athlon classic has it running at half core speed(i think) it's kinda late, i think someone will be able to describe it better than me

 

[heng1028]

for the amd processors the L1 cache is more than L2 cache while intel processors has more L2 cache than L1 cache.

will the more L1 cache of amd processors bring more performance than intel processors??

 

[AndyHui]

The L1 cache has a lower latency than the L2 cache. This means that data in the L1 cache can get to the execution units/pipeline faster than data coming from the L2 cache. In turn, these caches are far faster than system RAM.

The problem preventing L1 and L2 caches from becoming too large (apart from the silicon real estate) is that there are longer latencies involved with searching larger caches.

More L1 and L2 cache means that more data is stored in these fast memory areas, so the CPU needs to go to the slower system RAM less often.

So in the case of the Duron vs Celeron, although more data is available at hand in the L1 cache for the Duron, it may take a couple more clock cycles for it to be read than the Celeron. The Celeron has a bigger L2 cache because it has a much wider data path to the CPU, so again, the latencies and the speed at which the data in the L2 cache reaches the CPU is quicker.

You can't take the specs for the L1 cache on the Pentium 4 the same way though. Although it has only 8KB L1 cache, its architecture uses a different method of addressing data and instructions and uses what is known as a trace cache instead. Unlike ordinary L1 and L2 caches, the trace cache is located after the execution units. Estimates place the trace cache on the Pentium 4 to be somewhere around 96KB.

 

[heng1028]

that is mean there is an optimum size of cache in a processor??

too much is no good and too little is bad?? is that what you mean Andy??

more L1 cache will take longer time to read but why large L2 cache doesn't take longer time to read??

 

[AndyHui]

That's a simple way to put it, but yes. Too little is no good, too much and you get diminishing returns.

A larger L2 cache does take longer to read and decode addresses. In the Celeron's case, this is negated because of the wider data path.

The benefits of having a cache are obvious though. The original Covington Celeron without L2 cache, and the subsequent Mendocino Celerons are a perfect example of this.

 

[heng1028]

so in the case of duron and celeron, which will bring more performance in terms of cache and its designs?

 

[AndyHui]

Supposedly the Duron has a better setup since the L1 and L2 caches are exclusive. This means that data in the L1 cache is not duplicated in the L2 cache, giving an effective total cache of 192KB.

The Celeron uses an inclusive cache, where data/instructions in the L1 are also found in the L2, for an effective total of 128KB. However, for raw performance, it's very difficult for the Duron to beat the 256 bit wide data path to the caches that the Celeron has. The Duron only has a 64-bit wide path.

 

[heng1028]

how about P3 cumine and tbird??

 

[BurntKooshie]

I wrote this article over at systemlogic.net, but its down (for a little while), so I put it up here, temporarily

Its long. Quite long. But, I've had some very good feedback about it, so I guess it must be useful (a graduate course at the University of Tennesse used it for background info....).

Yes, I know, the 3 graphics in the article aren't there, but that's because I'm too ignorant too know how to put up an image, as I just saved the *.doc file, and saved as htm

Sorry for the shameless self plug, but I thought it would fit in....

 

[AndyHui]

Again, I would say that the P3 would have a better cache subsystem. Again, the CuMine uses an inclusive scheme and an exclusive scheme for the TBird.

Again, the data path is 256 bits wide for the CuMine and only 64 bits wide for the TBird. The L2 cache on the CuMine also has a lower latency than the TBird's L2 cache.

 

[AndyHui]

Thanks for that BurntKooshie....a better explanation than my clumsy attempt.

 

[heng1028]

thanks for your inputs

 

[BurntKooshie]

LOL....okay, I was working on the images (i suck at HTML), and I found out something: the page can load, with the pictures, in Opera 5, and Netscape 6, but NOT IE 5 GO figure....I made it with a MS product (in word, save *.doc as html), and guess what....IE5 can't see the pics