Unfortunately, I don't have a link to anything. I designed a gate-level adder in my VLSI class in college. Might have had a multiplier on there as well...actually, I htink I did. Not too difficult... depending on how many bits of multiplication you need. I can try to remember to dig up my circuit level schematic and at least give you the general idea of what was going on.
EDIT: when you say floating point, are you referring to a 32-bit number such as "floating point" generally refers to if I'm not mistaken. That will take a significant nubmer of gates!!! A 4-bit multiplier... not too many gates... a 32-bit... heheheeh... thats nutty. Anywyas... whether its 32 or 4 bits, the idea is just the same...
Do you want a verilog/vhdl model, or a schematic, or some form of pseudo schematic that shows a gate-level abstraction? I found a bunch of this stuff for Sohcan one night on ICQ... I can go look up the conversion in my logs and find the links.
The basic steps involved for floating-point arithmetic are the same regardless of the implementation....for example, to do a floating-point add, you have to align the mantissas based on the exponents, add the mantissas, re-normalize, then round. To do a floating-point multiply, you have to multiply the mantissas, add the exponents, re-normalize, then round.
The actual gate-level implementation depends on a number of factors...there's any number of different types of adders and multipliers that could be used....ripple-carry adder, carry-lookahead adder, carry-save adder, Manchester adder, Ling adder, etc. I guess it all depends on how much logic you want to use and how fast you want it to be. In addition, the stages and the multipliers (if a Wallace tree is used) can be pipelined to speed things up.
Check here, here, and here for some info on various adders and multipliers.