Question FYI - AMD to keep AM4 as a budget option alongside AM5. [JtC]

[VirtualLarry]

Interesting. Apparently from a Forbes interview with Robert Hallock.

Edit: Also, no DDR4 for AM5.

 

[JasonLD]

AM4 definitely could remain budget APU platform, but DDR4 availability and price in the future might be the most important factor for a longetivity of the platform.

 

[Insert_Nickname]

I don't see why not. It's a mature stable platform, and can use cheap DDR4.

If this means they keep supporting it, so much the better.

 

[NostaSeronx]

It is also the platform where GlobalFoundries will be mostly on. Since, AM5 is TSMC only.

 

[VirtualLarry]

It is also the platform where GlobalFoundries will be mostly on. Since, AM5 is TSMC only.

Clueless!

 

[GodisanAtheist]

Part of the reason I'm strongly considering an upgrade to a 5800x instead of Zen 4 is that I'd get to bring 32gb of mid tier DDR 4 memory along with me from and aging z170 platform.

Big platform upgrade with modern "amenities" going to B550, tons of extra performance, dirt cheap upgrade in the grand scheme of things with a used 5800x processor.

 

[Hans Gruber]

Part of the reason I'm strongly considering an upgrade to a 5800x instead of Zen 4 is that I'd get to bring 32gb of mid tier DDR 4 memory along with me from and aging z170 platform.

Big platform upgrade with modern "amenities" going to B550, tons of extra performance, dirt cheap upgrade in the grand scheme of things with a used 5800x processor.

You want the 5700x, not the 5800x. If you think you want the 5800x you want the 5900x. You also want to wait a few months for those prices to come down.

 

[NostaSeronx]

Clueless!

The decision to extend AM4's lifespan is more or less determined by extended/amended agreements with GlobalFoundries.

Existing products on AM4: Zen2 with GloFo IOD and Zen3 with GloFo IOD, prior Zen/Zen+ APUs

New product potential at GloFo with new 12nm FinFET process(related more to 14HP/7LP (MWF) than to 14LPP/12LP/12LP+ (SWF/DWF)):

Fin-shape Optimization for Single Diffusion Break Device Performance in FinFET Technology

Single diffusion break (SDB) devices in FinFET technology are desirable and attractive for their minimum footage in aggressively scaled circuits. This paper reports fin-shape optimization efficiently improved SDB PFET device performance by up to 9%. More importantly, it was found that the...

ieeexplore.ieee.org

A 12nm CMOS Technology on High Performance Multi-Workfunction Transistors

We present here a state-of-art 12nm FinFET technology with multi-workfunction gate stack for device improvement over single gate stack. The improved devices achieved +18% AC performance based on +24%/+12% NFET/PFET DC performance gain, as well as +24% SRAM FET performance improvement. Better...

ieeexplore.ieee.org

As AM4 exists below AM5, there will be need for Athlon-ification.
New AM5 products = Ryzen
New AM4 products = Athlon

AM4 first 5-years (Ryzen&Athlon) -> AM4 last 5-years (Athlon)+AM5 first 5-years(Ryzen)

GloFo has a wide 3D-stacking IP grasp:
DRAM-on-Logic (2015 TV)
SRAM-on-Logic (2017 TV)
Logic-on-Logic (2019 TV)

 

[Thibsie]

The decision to extend AM4's lifespan is more or less determined by extended/amended agreements with GlobalFoundries.

Existing products on AM4: Zen2 with GloFo IOD and Zen3 with GloFo IOD, prior Zen/Zen+ APUs

New product potential at GloFo with new 12nm FinFET process(related more to 14HP/7LP (MWF) than to 14LPP/12LP/12LP+ (SWF/DWF)):

Fin-shape Optimization for Single Diffusion Break Device Performance in FinFET Technology

Single diffusion break (SDB) devices in FinFET technology are desirable and attractive for their minimum footage in aggressively scaled circuits. This paper reports fin-shape optimization efficiently improved SDB PFET device performance by up to 9%. More importantly, it was found that the...

ieeexplore.ieee.org

A 12nm CMOS Technology on High Performance Multi-Workfunction Transistors

We present here a state-of-art 12nm FinFET technology with multi-workfunction gate stack for device improvement over single gate stack. The improved devices achieved +18% AC performance based on +24%/+12% NFET/PFET DC performance gain, as well as +24% SRAM FET performance improvement. Better...

ieeexplore.ieee.org

As AM4 exists below AM5, there will be need for Athlon-ification.
New AM5 products = Ryzen
New AM4 products = Athlon

AM4 first 5-years (Ryzen&Athlon) -> AM4 last 5-years (Athlon)+AM5 first 5-years(Ryzen)

GloFo has a wide 3D-stacking IP grasp:
DRAM-on-Logic (2015 TV)
SRAM-on-Logic (2017 TV)
Logic-on-Logic (2019 TV)

So ? lol

 

[NostaSeronx]

So ? lol

AM4 as a budget option is to primarily use GlobalFoundries.

Same timeframe:
~800K wafers of AMD's use of GloFo-14nm
~350K wafers of AMD's use of TSMC-7nm

A budget option generally indicates a higher volume. Of which, GlobalFoundries is vastly superior to TSMC.

AMD is required by the 2021 WSA to have NTOs in the second-half of 2023. With those products being pre-ordered having a two-year orderspan to the second-half of 2025.

AM4 turns to budget-parts going forward of which is done at GlobalFoundries.

Premium AM5 => Ryzen (TSMC 5nm => shrink scaling (1.5x cost per 2D-node))
Budget AM4 => Athlon (GlobalFoundries 12nm-MWF FF => 3D-stack scaling (0.8x cost per 3D-node))

Early portion of ELTS-AM4, selling high-cost at lower-margin => Later portion of ELTS-AM4, selling low-cost at higher-margin
Ryzen 3000/Ryzen 5000 => Will be replaced by GloFo CPUs on AM4 and succeeded on AM5 w/ pure TSMC.
Ryzen/Athlon 4000 => Will be replaced by GloFo APUs on AM4 and succeeded on AM5 w/ pure TSMC.

It has been confirmed by other sources that AM4 is going on for another five years. Of which, it is mostly going to be GlobalFoundries' show. Where TSMC is in process of being pushed to AM5.

Current to later:
AM5 TSMC to TSMC
AM4 TSMC to GloFo

The only reason AMD has specified for AM4's increased lifespan is obligation to GlobalFoundries. Of which, where Zen2/Zen3 scaled via 2D-shrink at TSMC, Zen2/Zen3 at GlobalFoundries scales via M3D-shrink:

Power, performance, and cost comparisons of monolithic 3D ICs and TSV-based 3D ICs

Power, performance, area, and cost analysis of TSV, mini-TSV, and monolithic 3D ICs is presented. Power savings for TSV, mini-TSV, and monolithic 3D ICs are 21%, 25%, and 37%, respectively, compared to that of a 2D IC. It is shown that monolithic 3D can deliver one node PPC benefit, whereas TSV...

ieeexplore.ieee.org

Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET technology

In this paper, we conduct a comprehensive design comparison of 2D ICs, monolithic 3D ICs and TSV-based 3D ICs using a silicon-validated 14nm FinFET foundry technology and commercial quality designs. Through full-chip layouts and sign-off analysis using commercial-grade tools, the potential of...

ieeexplore.ieee.org

A 14nm FinFET transistor-level 3D partitioning design to enable high-performance and low-cost monolithic 3D IC

Monolithic 3D IC (M3D) shows degradation in performance compared to 2D IC due to the restricted thermal budget during fabrication of sequential device layers. A transistor-level (TR-L) partitioning design is used in M3D to mitigate this degradation. Silicon validated 14nm FinFET data and models...

ieeexplore.ieee.org

etc.

Same performance or better performance at reduced cost but at higher profit.
7nm = 2.25x cost(full node addition of cost)
2x 12nm-M3D (12nm-2D to 12nm-3D=7nm-2D in PPA) = 1.5x cost(half-node addition of cost)

 

[NTMBK]

Makes sense, especially with the chiplet architecture. Keep using the AM4 northbridge from Zen 3, replace the CPU chiplets with Zen 4 ones. Easy upgrade product for the old platform, like the old Pentium Overdrive.

 

[Asterox]

Interesting. Apparently from a Forbes interview with Robert Hallock.

Edit: Also, no DDR4 for AM5.

Red is old news, this has been a known fact for a long time.

There were absolutely no reliable rumors that AM5 would support ddr4 memory.

In the future, hm i can see one new Zen 3 6/12 CPU with 3D V-Cache as final nail in AM4 coffin.

 

[gdansk]

Keep using the AM4 northbridge from Zen 3, replace the CPU chiplets with Zen 4 ones.

It sounds possible but why would they? Current Zen 3 chips with more price cuts would fit the budget line. The best bang for the buck Raptor Lake will probably be like the 12400F: $175 MSRP 6+0 or 6+4 configuration equipped with DDR4. A cheap enough 5700X could compete.

 

[maddie]

It sounds possible but why would they? Current Zen 3 chips with more price cuts would fit the budget line. The best bang for the buck Raptor Lake will probably be like the 12400F: $175 MSRP 6+0 or 6+4 configuration equipped with DDR4. A cheap enough 5700X could compete.

A 6nm compute chiplet has to be involved. You need all pricing advantages when going budget.

 

[LightningZ71]

So, the biggest question for AM4 is, if it is staying around for 5 years, and if the WA with GloFo still requires NTOs into next year, will AMD invest in actually porting Zen2 or later to a GloFo node?

I just don't see it making any sort of financial sense.

 

[LightningZ71]

A 6nm compute chiplet has to be involved. You need all pricing advantages when going budget.

I have hoped that AMD would see value in releasing an N6 shrink of the ZEN4 (meant zen3) CCDs in a follow on 5625x/5825x/5925x/5975x. They could opt for high density libraries to increase yield per wafer.

 

[maddie]

I have hoped that AMD would see value in releasing an N6 shrink of the ZEN4 CCDs in a follow on 5625x/5825x/5925x/5975x. They could opt for high density libraries to increase yield per wafer.

???? N6 shrink for Zen4? More like N6 expansion for Zen 4 CCDs, which are N5.

 

[Mopetar]

???? N6 shrink for Zen4? More like N6 expansion for Zen 4 CCDs, which are N5.

I'm assuming he meant Zen 3 based on using the 5000 series naming.

 

[jpiniero]

I'm assuming he meant Zen 3 based on using the 5000 series naming.

Yeah Zen 3. I don't see it. They'll continue to churn out more because of Milan but shrinking it to N6 seems like too much effort.

 

[NostaSeronx]

So, the biggest question for AM4 is, if it is staying around for 5 years, and if the WA with GloFo still requires NTOs into next year, will AMD invest in actually porting Zen2 or later to a GloFo node?

I just don't see it making any sort of financial sense.

GlobalFoundries:
- AMD is still planning to do stuff and recent WSA is acknowledgment of commitment.
- AMD will use both Dresden and Malta.
- AMD will do Datacenter, Personal Computing, Embedded, and other growth markets at GlobalFoundries

Budget falls under "HPC Microarchitecture" which is satisfied by Zen architectures. Some factor of cost-cutting without, decreasing performance and increasing power.

Backports have been hinted at before, but they were assumed to be a 2D die. However, these backports are likely to use Malta's 3D/M3D stacking tool-line. Where Zen2/Zen3 at TSMC were synthesized with 2D EDA tools, Zen2/Zen3 at GlobalFoundries will be synthesized with 3D EDA tools. The whole 3D-stack Logic-on-Logic was validated in 2019 and has been slated for HVM in 2021. It is unknown if it has been delayed or will be announced with products.

New 12nm process and techniques => lower process/tool/mask entry-cost than 7nm/6nm.

Reduced cost:
EPYC and Athlon(Athlon variants of Ryzen 3000-series and Ryzen 5000-series) => Same option of 4-Hi Stacked SRAM as well.

Bad example:
Athlon Zen2/Zen3 CPU @ GF12 FF => ~200 USD(8-core) versus 300+ USD(prior-variants)
-- Higher volume
-- Higher yield
-- Lower cost

Ryzen 3000X/5000X will still be available, but will maintain a higher cost with a slow price decline, with higher achievable performance via OC.
Athlon-variants at GloFo, will reduce the cost majorly and be negligible difference on Perf/Power/Area, with more focus on increasing stock/within TDP performance.

The bang for buck is within TDP, not outside it. OEMs would rather buy higher stock performance over expected higher overclock performance.

14LPP(SWF)
12LP(SWF), +10% performance (required a new tapeout to get all the performance)
12LP+(DWF), +20% performance (re-tapeout of new tapeout of above)
New 12nm FF 2022(MWF), +20% performance (definitely a new tapeout)

The above falls under GlobalFoundries' 3D-HPC strategy:
- Lower cost than 7nm.
- Reduction of lateral wire-length with addition of vertical wire-length.
- Increased performance and decreased power from newer tuned FinFETs.

AMD Zen2/Zen3 @ GlobalFoundries is cost-optimized and potentially sold where 2700X use to sell at in Mid-2019/Late-2019 (~$250/~$195). With most of the dies however servicing where EOL'd Naples in 2023 and EOL'd Rome in 2024 was. Larger volume at GlobalFoundries plus lower prices means more EPYC platforms/contracts.

There is also DDR4L which is derived off DDR4 3DS;
2014 =>

2018 =>

Slightly more advanced than standard 3DS, specifically with DRAM cell flipping like they(Samsung/SK Hynix/Micron) did with V-NAND.

So, there is still scaling on DDR4 available through advanced 3DS and DDR4L-spec. Allowing for more aggressive budget versions of Server OPNs (longer lifespan than standard Ryzen): https://www.phoronix.com/scan.php?page=article&item=amd-ryzen-server&num=1

Ryzen/TSMC Server (AM4) => Athlon/GlobalFoundries Server (AM4), where Ryzen/TSMC Server moves to AM5.
- More budget focus on CPUs, increased spending on DRAM/NVMe/PCIe.

 

[DrMrLordX]

AM4 definitely could remain budget APU platform

Which APU? Does Rembrandt have a DDR4 controller? I don't think it does.

 

[jpiniero]

The one thing AMD hasn't done yet is 8 core Cezanne/Renoir without an IGP. Anyone's guess as to whether they've actually been storing any for a release later.

 

[SteinFG]

The one thing AMD hasn't done yet is 8 core Cezanne/Renoir without an IGP. Anyone's guess as to whether they've actually been storing any for a release later.

I'm sure there's isn't any made. AMD wants to make a somewhat logical product stack, that's why they don't even offer R7 4700G in retail.

 

[LightningZ71]

It seems to me that anything larger than a quad core Zen2 chip would be prohibitively large on any of the GF 14LP/12LP/12LP+ nodes. I was rather surprised that AMD actually went with TSMC N6 for Mendocino initially, but, remembered that AMD already has all the modules done for that node (save for Zen2, which was a "relatively easy" shrink from the related N7 process. But, what does AMD do on a GF process that makes any financial sense? They can certainly continue to make the IO Dies for AM4. Unfortunately, their use almost requires a rather big and expensive AM4 package. Updating any part of the old Raven Ridge part would require significant R&D expense as there's no newer IP ready for those nodes. They could possibly update Dali (Zen1+ 2/4, 3CU Vega 1st gen) to 12LP+ for better power savings and higher transistor density for better wafer yields for the very bottom of the market, but, that product is just way WAY behind at this point.

Maybe something for the embedded market?

 

[NostaSeronx]

But, what does AMD do on a GF process that makes any financial sense?

Related old GloFo roadmap:


12nm FinFET - 2023-2025 => ~3500-3700 USD at GloFo.
7nm FinFET - 2023-2025 => ~9000+ USD at TSMC
5nm FinFET - 2023-2025 => ~13000+ USD at TSMC
3nm FinFET - 2023-2025 => ~18000+ USD at TSMC

R&D of NTO on 12nm => ~$100M
R&D of NTO on 7nm => ~$300M
R&D of NTO on 5nm => ~$550M

Addition of 3D-NTO for 12nm => ~$130M (no matter how much layers added, the cost for AMD is fixed regardless of layer count on R&D)
Single-layer 12nm ('23-'25) => 3500-3700 USD
Two-layer 12nm => 4500-4700 USD
Three-layer 12nm => 5500-5700 USD
Four-layer 12nm => 6500-6700 USD
Five-layer 12nm => 7500-7700 USD

2016-2017 14nm => ~8000 USD

AMD's target with GlobalFoundries is to reduce cost.
12nm - 1 layer => Behind 7nm
12nm - 2 layer => Equal to 7nm node || 0.5x cost of 2D-7nm
12nm - 3 layer => Equal to 5nm node || 0.4x cost of 2D-5nm
12nm - 4 layer => Equal to 3nm node || 0.35x cost of 2D-3nm
12nm - 5 layer => Equal to 2nm node

It is very specifically meant for AMD's HPC microarchitecture. Which is likely macro-sliced or whatever Zen(x) on 12nm-3D. With the performance of Zen2/Zen3, but with reduced cost. Allowing for 5x00X/3x00X/2x00X-like performance at a significantly lower price point. AM4 will continue to get products, but they will return the entire stack back to GlobalFoundries.

2015 plan for 2017 AM4:
Summit => GlobalFoundries
Raven => GlobalFoundries
Bristol => GlobalFoundries
Stoney => GlobalFoundries


2023-2025 transitions from TSMC products back to GlobalFoundries products.

AM5 => TSMC-only, Higher ASP with higher than expected performance jumps.
AM4 => Transitions back to GloFo-only, Lower ASP with expected performance jumps.

AM4 GloFo Strikes Back edition is split in two architectures:
HPC at Malta-3D; Increased area density/perf at lower cost relative to TSMC-variants => High price point (~$200) ~ Budget-market
ULP at Dresden-2D; Significant decreased costs for low-cost markets with AM1(Bhavani) & FM2+(Carrizo[A8-7680/A6-7480]) target. => Low price point (~$50) ~ Ultra-budget-market

Specifically 3D-HPC (3D-Zen);

12nm 7.5T/84CPP/64Mx
7nm 6T/57CPP/40Mx+57Mx
For two-layer(same lib as prior 12nm; no idea if new 12nm has new denser libs):
Most optimistic =>
12nm-3D virtually is 3.75T/42CPP/32Mx (There is plenty of strategies of getting 0.5X*0.5Y shrink w/ 2Z expanded)
Least optimistic =>
12nm-3D virtually is 5.6T/63CPP/48Mx + 3rd layer => 4.2T/47CPP/36Mx

GloFo-3D(TSV)&M3D(MIV) production-ready showcase: January 2023 to June 2023, customers receive their orders in "Early 2023"

They could possibly update Dali (Zen1+ 2/4, 3CU Vega 1st gen) to 12LP+ for better power savings and higher transistor density for better wafer yields for the very bottom of the market, but, that product is just way WAY behind at this point.

If they did that, it would NOT be 12LP+, but this node: https://ieeexplore.ieee.org/document/9771014

14LPP/12LP/12LP+ => Doped Fins for sLVT/LVT/HVT.
The above node follows 14HP and 7LP => Undoped Fins for sLVT/LVT/HVT.

There however is no planned RTOs, the only plan is NTOs.

A lib-shrink/optimization of Raven2/Dali is unlikely, a project with the scope of Monet however is likely to pop-up.

With 3D-TSV/3D-MIV being used together, as that is the most advanced option succeeding standard 12nm;
2-layer CPU (MIV-interconnect + TSV) <-- CPU Hottest so closest to heatsink:: Zen3-esque target
2-layer GPU (MIV-interconnect + TSV) <-- GPU Middle do to low-leak:: RDNA2-esque target ==> Re-used as RX6100/RX7100
IOD (TSV-interconnect) <-- IOD is bottom


~~~~~~~~
Prior WSA => "Revenue-centric" - pay more for shrinks
Current WSA => "Volume-centric" - pay less for more volume, the current metric hitting GlobalFoundries is low-utilization rate. Low-util rate means higher fab upkeep costs.

AMD's 2011-2015 3D roadmap, likely revived since node shrinks at GloFo beyond 12nm/11nm are far away till something replaces 193i:
CPU-first:
3D-CPU for Malta (cheaper than 7nm, standard perf up(Zen2/Zen3 => 5-7% increase in perf for 12nm 3D)
2D-CPU for Dresden (heavy cost cutting: 12nm Quad+ RISC-V P710/ARM A710+Custom clones)

GPU-second:
New IOD following AM5's strategy, but rather than having a in-tile GFX, it will be on-tile GFX. Potentially, IO+GFX would be re-used for low-end/budget GPU. || Malta
2D-CPU will have a 2D-GPU w/ 3D-DRAM in 2.5D(APU-function), but will be even lower-end/ultra-budget for AIB(GPU-function). || Dresden

APU-last:
3D-CPU stacked over IO+GFX tile || Malta
2D-CPU+2D-GPU includes CPU or GPU IO in Version2 bottom die(true-APU function). || Dresden

Mature node (GF-only) => Mature platform
Bleeding node (TSMC-only) => New platform



New designs+new innovations is the expected iterative design focus.
TSMC|AMD|AM5 = Maximum budget($$$), maximum (above industry) performance increase
GF|AMD|AM4 (HPC) = Reduced budget($$), expected (at industry) performance increase
GF|AMD|AM4 (ULP) = Lowest budget($), good-enough (below industry) performance increase for below expected TDP/PPT(above industry).

New products as stated before will be there for AM4. Of which, Zen-category will be cheaper than previous iterations (compared to: Ryzen-7nm), and below Zen-category will be even cheaper (compared to: Ryzen-14nm/Ryzen-6nm).

Also, as we approach the launch of ULP:
ULP1 Micro-architecture(2023-12nm) => Cluster-based :: iCore - ILP/TLP & fCore - ILP/TLP/DLP(ST gets faster big SIMD)
ULP2 Micro-architecture(2025-11nm shrink) => Grid-based :: mCore - ILP/TLP/DLP

Example of Grid;
Standard Arch Integer: 2x 64-bit sALU + 1x64-bit IMUL + {2x 128-bit VALU + 1x 128-bit VIMUL} cannot be used for ILP.
Grid Arch Integer: 2x 64-bit Control ALUs(ILP or TLP) + 2x 64-bit ALUs(ILP/TLP/DLP) + 2x 64-bit ALUs(ILP/TLP/DLP) + 2x 64-bit IMUL(ILP/TLP/DLP)
Left-half gets PRF0, Right-half get PRF1:: same to less function units of standard arch, but better utilization of ILP Superscalar or DLP SIMD if program swings either way. TLP in case ILP/DLP isn't exploited, as well. ~90+% work efficiency(unit efficiency) on normal real world programs.
Compute programs = ~42% Integer Scalar + Packed, with more focus towards Scalar(~70%) over Packed(~30%). Scalar-compute is currently executed on the fCore not the iCore, locking out big perf increase of OoO-ILP optimization. As the iCore is ILP-focused, while the fCore is DLP-focused. Hence, the focus of a mixed-point grid-architecture core, which can focus on both.
64-bit GPR+128-bit Packed (64-bit PRF0+64-bit PRF1) => much more efficient than 64-bit GPR PRF0 + 128-bit Packed PRF1. It also can scale well with 64-bit FP+128-bit VFP(64-bit PRF2+64-bit PRF3).

With HPC, being the key high ASP part on AM4; HPC1/HPC2/etc would be 2-layer/3-layer/etc being stacked monolithic.

AM5 {
Path1. (Performance-orientated) TSMC shrink-scaling => 2D Standard(Zen) Architecture (Increased cost input, requires higher ASPs)}
AM4 NPI-post TSMC to AM5 {
Path2. (Power-orientated) GlobalFoundries stack-scaling => 3D Standard(Zen) Architecture (Reduced cost input, reduce need of higher ASP)
Path3. (Pervasive-orientated) GlobalFoundries cost-scaling => 2D Non-standard(a.k.a. Not Zen) Architecture (Maximize energy/area/cost, lowest cost input, ultra-low ASP but better profit-margin)}

CPU-side, majority of configurations + price:
AM5 New TSMC-HPC(Zen) = 105W-170W TDP (~142W to ~230W PPT) == $$$ -- ~$650 (CPU+Mobo) <== Highest revenue for single unit
AM4 New GF-HPC(Zen) = 35W-65W TDP (~47W to ~88W PPT) == $$ -- ~$250 (CPU+Mobo)
AM4 New GF-ULP(Not) = 5W-25W TDP (~7W to ~34W PPT) = $ = ~$75 (CPU+Mobo) <== Highest revenue for total market

AM4 Ryzen Server (upper-band ASP) -> AM5 Ryzen Server (Top-tier HPC/Zen @ TSMC)
AM4 Ryzen Server (middle-band ASP) -> AM4 Athlon Server (Budget-tier HPC/Zen @ GF)
Prior Opteron (lowest-band ASP, pre-AM4) -> AM4 Opteron Server (Ultra-budget-tier ULP/Not Zen @ GF)

AM4 as budget/ultra-budget has a side benefit(unrelated) of going against the international-versions sockets of;
Huawei/Hisilicon Kunpeng Desktop (Most recent re-org is to focus on Desktop and Laptop, reducing funding for Server and Mobile)
Zhaoxin LGA-socket Desktop
Starfive JH-Supreme-CPU Desktop

Lower cost + Lower Power => Lower barrier of more than one PC per household + person.

GlobalFoundries not-capable of funding tailored bleeding edge nodes => GlobalFoundries capable of funding tailored nodes

Using ARM's Cortex A-M3D two-layer architecture as a guide by folding the core based off the L2 cache.

~44 mm2 with 4-cores => 8-cores
Assumption is that they keep 10.5T/9T and not use a more dense tailored library.

The L3 can be folded in a way to have 8 MB in 4 MB of L2. So, the output is capable of 8-cores within ~33 mm2. ~50mm2 to ~68 mm2 is a safe bet.

A smaller die can help punch down on the costs. Example:
16-core Athlon Platinum = ~3xx USD
12-core Athlon Platinum = ~2xx USD
8-core Athlon Gold = ~1xx USD
6-core Athlon Gold = ~1xx USD

Re-iterate once again there are newer 12nm FinFETs;
- Higher Yield
- Lower Variation
- Higher Perf
- Lower Power
~https://ieeexplore.ieee.org/document/9771014

GlobalFoundries petty much stated if they aren't shrinking, they would move to stacking.
2012 - 3D Stacking planning included into Malta
2013 - EUV shrinking planning included into Malta
2015-2016 - Mono3D/M3D/Sequential Stacking is adopted for aggressive Logic-on-Logic.
2018 - EUV is dropped
2019 - 3D Stacking becomes major focus.

AM4 without something new, cuts its demand down. With AM5 targeting higher power targets, AM4 would have to target lower power to not compete.

Prior WSA:
Phase one = First half-2023 existing products
Phase two = Second half-2023 existing and new products (shared minimum annual floor)

Latest WSA:
Phase one = First half-2023 existing products
Phase two = Second half-2023 existing products
Phase three = Second half-2023 new products (independent annual floor)

The WSA also indicates the removal of movement across standard nodes, instead prioritizing tailored nodes.
Prior-roadmap: Standard node -> Tailored node -> Standard node -> Tailored node
Latest-roadmap: Tailored node -> Tailored node -> Tailored node -> Tailored node
Since, majority of AMD's revenue isn't being attributed to a fraction of required CapEx for 7LP/5LP/3LP.