- Jul 3, 2005
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I had a little time on my hand between busy spells, so I took a little time to draw up a rough design schematic for a future microarchitecture, which I originally posted on Anandtech a few days ago. Hopefull, I can spur up some good, in depth, and substantive conversations about microarchitectural trends in the next period of time in terms of general purpose ICs. Although it would be most beneficial and interesting to those actively study and do research in the area(like myself) or make a living in this field, I'm sure many self trained computer architecture enthusiast have plenty to contribute to a meaningful discussion as well.
This is a conceptual design that incorporates a number of likely trends in future commercial microarchitectures in the next number of years. It is actually roughly based on a commercial microarchitecture that might be coming on market in the near to medium term (depends on what you consider "near"); but I have altered, omitted, and replaced a number of architectural elements and mechanisms so that nothing useful in terms of the original design or specifications could be deciphered, while still ending up with a functional conceptual design. The really important things are useful concepts and trends in designs anyway.
http://farm3.static.flickr.com...71934_3c430e8bf3_b.jpg
Or here link to a larger version:
http://news.webshots.com/photo...4584010090923268CSKvKF
This deign is emblematic of some classes of new features that might be heavily incorporated for increased ILP and lower thermal consumption / instruction throughput, design concepts that take into account of: how best to blanance physical RF latency vs. size vs. #ports trade off; how to deal with long latency instructions and their dependents especially when it comes to misses beyond the private cache of the core; dependence steering of instructions based on register dependency graphs; the related concept of the use of clustered FUs and their; as well as companion techniques to clustering such as banked way predictions and independent LSQs; and a number of other trends.
I'll be glad to provide any answers to general and specific questions provided that they are within ethical bounds; which means that there are things that I will have to be silent on. But hopefully there will be interest, and this maybe a starting point for some substantive discussion involving many people here.
If people have trouble seeing the overall schematic, here are higher res quadrant views:
http://farm3.static.flickr.com...48484_6dcc4ed75b_b.jpg
http://farm3.static.flickr.com...51718_a0fe9349ab_b.jpg
http://farm3.static.flickr.com...57575_438c79acf0_b.jpg
http://farm3.static.flickr.com...61925_168baa3a42_b.jpg
This is a conceptual design that incorporates a number of likely trends in future commercial microarchitectures in the next number of years. It is actually roughly based on a commercial microarchitecture that might be coming on market in the near to medium term (depends on what you consider "near"); but I have altered, omitted, and replaced a number of architectural elements and mechanisms so that nothing useful in terms of the original design or specifications could be deciphered, while still ending up with a functional conceptual design. The really important things are useful concepts and trends in designs anyway.
http://farm3.static.flickr.com...71934_3c430e8bf3_b.jpg
Or here link to a larger version:
http://news.webshots.com/photo...4584010090923268CSKvKF
This deign is emblematic of some classes of new features that might be heavily incorporated for increased ILP and lower thermal consumption / instruction throughput, design concepts that take into account of: how best to blanance physical RF latency vs. size vs. #ports trade off; how to deal with long latency instructions and their dependents especially when it comes to misses beyond the private cache of the core; dependence steering of instructions based on register dependency graphs; the related concept of the use of clustered FUs and their; as well as companion techniques to clustering such as banked way predictions and independent LSQs; and a number of other trends.
I'll be glad to provide any answers to general and specific questions provided that they are within ethical bounds; which means that there are things that I will have to be silent on. But hopefully there will be interest, and this maybe a starting point for some substantive discussion involving many people here.
If people have trouble seeing the overall schematic, here are higher res quadrant views:
http://farm3.static.flickr.com...48484_6dcc4ed75b_b.jpg
http://farm3.static.flickr.com...51718_a0fe9349ab_b.jpg
http://farm3.static.flickr.com...57575_438c79acf0_b.jpg
http://farm3.static.flickr.com...61925_168baa3a42_b.jpg