FSB - Integrated Memory Controller

[2ManyOptions]

Hi all,
I am bit new to this stuff and to this forum,but very much interested in it.

Currently Intel architecture uses FSB to talk to the NorthBridge from the CPU. With Nehalem I assume they are moving the memory controller onto the die itself.
- How different is this when compared to AMD's HT strategy?
- Also how is this helpful exactly? Because if the CPU has a cache-miss and has to access a chunk of data from RAM, it will have to talk to the RAM obviously,so how does the HT/on-die memory controller help in this matter?

Correct me if I am wrong, thanks in advance!

 

[Borealis7]

are you enzAviator on a different account?

1 post, more AMD/Intel questions.........smells fishy to me

 

[j0j081]

nevermind. free bump instead.

 

[2ManyOptions]

Thanks for the very informative and helpful reply, am quite sure now that I have posted in a very wrong place.

 

[Denithor]

You will get better responses if you pose this question in the Highly Technical forum.

 

[sutahz]

That question should be posted in the Highly Technical forum if you want a good response.
Yes it does appear to be EdzAviator (a day after his week long ban begins).
We can type 'bump' to get a msg moved up right, we could have a 'drop' msg too to request a moderator files the thread on like page 10 or so.

/drop

>>>>>>>
Hi all,
I am bit new to this stuff and to this forum,but very much interested in it.
(who actually says this??)
Currently Intel architecture uses FSB to talk to the NorthBridge from the CPU. With Nehalem I assume they are moving the memory controller onto the die itself.
(What brought about this assumption? It is documented though.)
- How different is this when compared to AMD's HT strategy?
(how would we know, its not even in production yet, i remember making that comment to EdzA as well)
- Also how is this helpful exactly? Because if the CPU has a cache-miss and has to access a chunk of data from RAM, it will have to talk to the RAM obviously,so how does the HT/on-die memory controller help in this matter?
(this example isnt related to the first part of your question. Whether the memory controller is on the die or the northbridge if a cache-miss does occur then either system will have to retrieve that information from the RAM.)

Correct me if I am wrong, thanks in advance!
(cant correct you on anything. You made 2 comments on basic things and asked 2 questions.)

 

[justly]

Nice witch hunt guys, someone could have tried to answer his question and checked out his response before you made unsubstantiated accusations.

For those of you recommending he post in the "highly technical" forum please look at that forum again, its more of a science (fiction) free for all than a place to ask an actual computer related question.

2ManyOptions, if your still reading this after all the "helpful replies" that you received let me try to give you another "helpful reply".
HT has very little to do with memory access in a single socket system. The on-die memory controller communicates directly with memory thereby reducing latency by not requiring a north bridge chip to redirect a memory request. The exact difference between Intel and AMDs on-die memory controller is not known, but I would assume it will be quite similar.

 

[cprince]

Here is the answer:

Moving the memory controller to the CPU die helps with memory latency. With Intel's current FSB scheme, the memory traffic is shared with PCI-e (graphics) and Southbridge(USB, PCI, SATA, IDE, etc...) traffic. The Northbridge decides which traffic can use the FSB at a particular time(whether it is memory, graphics, or southbridge traffic). When the memory controller is on the CPU, then the memory traffic goes straight to the CPU. This is the same as AMD's HyperTransport, in principle. In practice, the electrical properties might be different.

 

[2ManyOptions]

Thanks guys !

So moving the memory controller onto the die will help reduce memory access latency and the FSB will cease to exist.
Ok, now for the Southbridge/PCI/Graphics Card communication part, still it will be something like FSB? Because these still remain where they are right? To elaborate a bit on that (in a VERY crude way) I am moving my Northbridge onto the die => no concept of Northbridge(MCH)/Southbridge(ICH) => Just-1-Bridge(?) which will be what the only component to co-ordinate with the IO/PCI etc stuff?

That was horrible I guess but pls co-operate

 

[hans007]

according to the roadmaps

the high end nehalem will have a 3 channel IMC, the midrange a 2 channel and the low end one which has like 500 less pins on its socket will use a chipset (the advantage there is it can still use ddr2)

 

[justly]

"So moving the memory controller onto the die will help reduce memory access latency and the FSB will cease to exist."

You could say that (keep reading)

"Ok, now for the Southbridge/PCI/Graphics Card communication part, still it will be something like FSB?"

Yes, in AMDs case this would be the Hyper transport link.

"Because these still remain where they are right? To elaborate a bit on that (in a VERY crude way) I am moving my Northbridge onto the die => no concept of Northbridge(MCH)/Southbridge(ICH) => Just-1-Bridge(?) which will be what the only component to co-ordinate with the IO/PCI etc stuff?"

The only thing bing moved to the CPU is the memory controller so unless the southbridge is changed to also include the graphics interface there will still be two chips in the chipset (a traditional southbridge and a stripped down version of a northbridge that is only used as a graphics interface). You do have the right idea though.

Seems sad no one else is willing to help you.

 

[myocardia]

Originally posted by: justly
The only thing bing moved to the CPU is the memory controller so unless the southbridge is changed to also include the graphics interface there will still be two chips in the chipset (a traditional southbridge and a stripped down version of a northbridge that is only used as a graphics interface). You do have the right idea though.

Almost. The northbridge will still do everything a northbridge does now on current Intel chipsets, except the memory access. In other words, it will still be in charge of not only interfacing with the graphics subsystem through the PCI-E bus (actually, anything at all on the PCI-E bus), but also the processor and the southbridge.

And southbridge chipsets communicate with everything else in the system, like any PCI cards, nearly all onboard peripherals (most use the PCI bus), all IDE & SATA devices, etc.

Seems sad no one else is willing to help you.

Hey, we were just letting you handle it. You were doing just fine, I thought.

 

[2ManyOptions]

Okie, 1 more question ...
With the memory controller on-die you still need an interconnect between that and the memory sybsystem. So that is something that will be new with Nehalem then? (And AMD too will be having something like that...)

Thanks .

 

[myocardia]

All AMD processors already have that direct link between memory and the memory controller, and yes, Nehalem will also have to have one.