FSB & bus speeds? ::::

[househead]

Why is it that sometimes it says 133 Mhz bus and sometimes 266?

Or is it 133 Mhz and 266 MB of transfer?

Does all the PCI slots share the same bandwidth?

What are harddrives unable to keep up with the speeds & bottleneck's the system?

thanks ;-)

 

[AndyHui]

In the case of the EV6 bus used on AMD processors, the nominal speed is 133MHz, but since it is a DDR bus, it results in a 266MHz speed.

What do you mean by PCI slots share the same bandwidth? All PCI slots in a system share the same 133MB/s bus back to the SouthBridge of the chipset.

Hard drives physically cannot transfer more than 40MB/s or so of data. In terms of computer speeds today as compared to RAM, that's quite slow, since RAM transfers data in the range of GB/s.

 

[househead]

For the processor, being a 266Mhz FSB, how much (in Megs) can it transfeR?

 

[AndyHui]

2.1GB/s

 

[househead]

How was 2.1 GB/s derived from 266 Mhz ?

*just curious*

Does the AGP share the PCI bus also?

Does the IDE channels share the PCI bus?

Is there anything that'll eventually slowly replace the PCI slot?

 

[AndyHui]

The EV6 bus is 64-bits wide. At 133MHz, DDR (that's where the x2 comes from),

64 bits x 2 x 133MHz = 8bytes x 2 x 133000000Hz = 2100 megabytes per second (MBps) or 2.1 gigabytes per second (GBps).

The AGP is on a different bus completely separate from PCI.

IDE channels are PCI devices, but do not share PCI bus bandwidth (anymore).

NGIO or perhaps PCI-X are going to eventually replace PCI.

 

[househead]

Thanks fer da explanation andY!

one last ques. ::: where is the x2 coming from? ;-)

 

[FooDog]

I assume you are talking about the 2x AGP? It is basically a simple way to account for port legacy based on the first AGP interface [which really isn't a bus, but a port, but that's not relevant here]. The first AGP interface was basically based on PCI, but unlike PCI, it allowed for full uise of the system bandwidth. 2x AGP made uses special signaling that allows twice the transfer rate over the port. It functions very much like DDRRAM which sends information on both the rising and falling edges of the clock signal. The current AGP level, 4xAGP, performs four transfers per clock cycle. The 8xAGP interface is due some time next year and will provide a zooming 4,068 MB/s of bandwidth.

 

[househead]

I meant the x2 from his calculation above about the PCI Bus

AGP 8x is def. something nice to look forward to....

dam, serial ata, agp8x, pci-x, makes me feel bad makin' a system now, knowing it's gonna be obsolete soon ;-)

 

[rommel]

its the way data is transferred on the sign wave of ddr sdram...one the rise and fall of the wave signal so it gives you twice the transfer of normal pc133 thus x (times) 2 or x2

 

[EdipisReks]

Andy's explanation above was for the processor's front side bus, not the pci bus. the 2x is because the ev6 bus type is ddr. on a ddr bus, information is sent on both the rising and falling edges of the cycle, instead of just the rising edge like in a traditional front side bus. in theory you get twice the throughput, but in actuality is is often quite less, depending on the application.

--jacob