The Everest shot is quite telling. For folks who missed from above,
http://www.ocztechnologyforum....om_3500MHZ_everest.png
A few observations:
1. If we compare the L2 and L3, the L3 is approx. half the speed of L2 when it comes to Write and Copy. However, for some reason the Read bandwidth shrinks to 1/3.
2. The slow Read bandwidth of L3 somehow looks to match the memory Read performance. This gives me an impression that the memory Read performance would be linear to the Read performance of L3.
3. Looking again, all memory performance seems to relate to L3 performance, except the latency. (Read=Read, Write=2xWrite, Copy=Copy)
4. If that's the case, what dictates the Phenom performance could be the slow L3, except where random access matters (latency of L3 is still decent).
5. Phenom's L1/L2 performance is at least x1.5 that of A64 and about equal to that of Core 2. (perhaps thanks to the 128bit execution units vs 64bit?)
6. If L3 is what holds Phenom's performance, it makes perfect sense that AMD is enhancing the L3 with upcoming Shanghai. It reportedly will have 6MB shared L3. (vs. 2MB of Barcelona)