First Steamroller processor core exposure

[csbin]

http://www.xtremesystems.org/forums/showthread.php?286242-Steamroller&daysprune=30

Integer scheduler / computing part, there are many things are doubled :whiste:

 

[R0H1T]

there are many things are doubled :whiste:

I'm hoping that the next round of gains, piledriver to steamroller, will be equally as impressive as was the case last time i.e. BD to PD :awe:

 

[Maximilian]

Would like to see benches of these things soon

 

[inf64]

Hans de Vries posted his thoughts on SA forums.
Also interesting dissection done at B3D by 3dilettante.

Looks more than legit but anything is possible. Major changes to the front end,integer and fp clusters of the core. Doubled ALU/AGU in integer section,double decoders, 2x FP units (connected with latest SOG update for 15h that references true 256bit pipelines in next gen core ).

 

[ShadowVVL]

But when do we get it?

I wanna go green! but if its 2014 forget it.

 

[csbin]

But when do we get it?

I wanna go green! but if its 2014 forget it.

Kaveri APU in 2013 Q4

 

[NTMBK]

I'm kind of curious how they managed to get a die shot that high quality this early on. I'm tempted to assume that its a fake for now- it's just a bit fishy smelling.

 

[inf64]

Sure it's fishy but it's not easy to make such a good fake and fool two guys like Hans and 3dilettante. I guess anything is possible though.
The reference to true FP256bit pipelines is true tho, it's in the latest AMD's 15h SOG manual .

 

[frozentundra123456]

Kaveri APU in 2013 Q4

Maybe, but wasnt Richland supposed to be out in March, and we still havent seen it.

 

[inf64]

AMD said that desktop richland is June from start. Mobile is already available in some notebooks.

 

[ShintaiDK]

Maybe, but wasnt Richland supposed to be out in March, and we still havent seen it.

Maybe they count paper releases as release

 

[podspi]

Correct me if I'm wrong, but did Hans post imply a move to SMT? I wonder if this means AMD will drop down to 8T/4C like Intel, or whether we'll be getting 16T/8C monster chips. (Assuming it actually works of course).

 

[Abwx]

Given all the supposed additions it could be an early enginering sample
of Excavator , i doubt Steamroller will bring that much mods.

 

[SocketF]

Correct me if I'm wrong, but did Hans post imply a move to SMT? I wonder if this means AMD will drop down to 8T/4C like Intel, or whether we'll be getting 16T/8C monster chips. (Assuming it actually works of course).

As far as I understand it, it seems like SMT from the L1D-cache point of view (the cache is shared between 2 threads), but rather like CMT from the AGU/ALU Point of view, as these units seems to be doubled, i.e. each thread would have its own, dedicated execution units.

Given all the supposed additions it could be an early enginering sample of Excavator , i doubt Steamroller will bring that much mods.

Yes probably, but don't forget that Steamroller's slogan on the Bulldozer roadmap is "greater parallelism" ...

 

[NTMBK]

Yes probably, but don't forget that Steamroller's slogan on the Bulldozer roadmap is "greater parallelism" ...

Hrrm. That is true...

Kind of an interesting idea- Kaveri with 2 modules, 4 cores, 8 threads.

 

[vltra]

Found this , does it make any sense?

 

[Ventanni]

Who cares about die shots, I want benchmarks!

 

[inf64]

Found this , does it make any sense?

Yes those are roughly the parts of the module. Notice 4ALUs and 4AGUs, double sized FP units (2x256bit FMA or maybe 4x128bit FMA). It makes sense that integer cores themselves (within the module) are organized as two groups of 2AGUs and 2ALUs and that each integer core can run 2 threads ( it has it's own dedicated decoder now). The whole module can be as NTMBK noted a 2C/4T capable "machine" (including the shared L2 of course). It's also a presumtion AMD needed and has implemented 256bit L/S capability in each integer core and 256bit dedicated bus from each integer core to the now doubled up FP unit. It all fits the "greater parallelism" they noted on the slides but should in reality bring some big performance gains especially since the starting point (BD/PD) has a huge room for improvement.

 

[Arachnotronic]

Erm, Hans seems to not be familiar with this:

2x128bit FMACs, not 2x256bit, although the "doubled up" FPU resources on the die-shot would suggest otherwise. Calling fake/manipulated on it? There's just no way AMD went ahead and dramatically redesigned & validated the SR core in such a short amount of time, especially given the layoffs/budget cuts.

 

[Abwx]

Yes probably, but don't forget that Steamroller's slogan on the Bulldozer roadmap is "greater parallelism" ...

Yes and Excavator is dubbed "greater performance" wich
is more in line with the mods , particularly the doubling
of execution ressources.

 

[vltra]

It seems fake , i mean it's a huge core . Doubling so many parts must require A LOT of transistors . 32 nm to 28 nm can't possible give them enough space . It's either this , and 2 module at most in an APU OR a design much closer to Piledriver , otherwise i can't image an APU with 3 modules . It seems very far fetched , but could this possibly be Excavator on 20 nm?

 

[inf64]

Erm, Hans seems to not be familiar with this:

2x128bit FMACs, not 2x256bit, although the "doubled up" FPU resources on the die-shot would suggest otherwise. Calling fake/manipulated on it? There's just no way AMD went ahead and dramatically redesigned & validated the SR core in such a short amount of time, especially given the layoffs/budget cuts.

What we will get in Q4(or Q1) is labeled as Kaveri2.0 . It's in resumes of SoC project managers in AMD (projects that started in 2010 btw and finished in 2013). My guess is that Kaveri2.0 is EX core based since original Kaveri1.0(SR based) should have launched in Q1 of this year and we never saw it. We saw a bump in the roadmap and we might get a Kaveri2.0(EX core or SR++) roughly 9 months to 1 year later.From BD to PD we had similar time gap.

Also it's very important to note that AMD's latest SOG for 15h generation of chips mentions (for the first time) a 256bit operations being done on a true 256bit pipelines. There is no such thing in the above slide you posted unless AMD "sandbagged" badly and misrepresented @ HC what those FMACs can do(which I seriously doubt).

 

[Arachnotronic]

What we will get in Q4(or Q1) is labeled as Kaveri2.0 . It's in resumes of SoC project managers in AMD (projects that started in 2010 btw and finished in 2013). My guess is that Kaveri2.0 is EX core based since original Kaveri1.0(SR based) should have launched in Q1 of this year and we never saw it. We saw a bump in the roadmap and we might get a Kaveri2.0(EX core or SR++) roughly 9 months to 1 year later.From BD to PD we had similar time gap.

Also it's very important to note that AMD's latest SOG for 15h generation of chips mentions (for the first time) a 256bit operations being done on a true 256bit pipelines. There is no such thing in the above slide you posted unless AMD "sandbagged" badly and misrepresented @ HC what those FMACs can do(which I seriously doubt).

Uh, links to both resumes and the 15h manual?

 

[mrmt]

It seems fake , i mean it's a huge core . Doubling so many parts must require A LOT of transistors . 32 nm to 28 nm can't possible give them enough space . It's either this , and 2 module at most in an APU OR a design much closer to Piledriver , otherwise i can't image an APU with 3 modules . It seems very far fetched , but could this possibly be Excavator on 20 nm?

Not only that, what's the TDP of such a big chip? 200W?

 

[Abwx]

There are questions that are not really questions...