Fetch, Decode, Execute cycle

[Fistandantilis]

OK, well I am studying the Concepts of Computer Organization and Architecture, and I am a bit confused about this cycle.

Heres what I need clarified,
The Fetch, Decode, and Execute cycle happens once for every iteration of the clock cycle.

and to really break it down that means,

A chip that has 10 cycles per minute, will perform 10 and only 10 Fetch, Decode, and Execute cycles per minute.

thanks for any help.

 

[TuxDave]

Well, based on what you said I'm assuming they haven't gotten into pipe stages yet. In the simpliest terms....

So when the first clock cycle occurs, it will do a fetch meaning it'll go to whatever program it's running and grab the next line of code. After fetching it, it will decode it to figure out what the line of code is supposed to do. Then after it figures it out, it does that action (add, multiply, if then else... etc..). Then that line of code is done.

Then it'll repeat that in the next cycle with the next instruction that it needs to execute. So essentially in each minute it will finish doing 10 instructions.

 

[Furen]

It sounds to me like you have a 3 (should be 4) stage pipeline (it could be, like Dave said, that you're not dealing with the pipeline at all yet since most modern CPUs split each of these three basic stages into smaller ones).

The Fetch stage is the point during which the CPU fills its internal buffers with instructions. The decode stage is where the CPU translates the code into something that can actually be executed by the execution units (instead of having each unit decode each instruction they're all predecoded). The Execution stage, I'm sure, is pretty self-explanatory. The one stage that you're missing is the write stage, which is the stage during which the execution core outputs its results back to your cache/buffers. This is the "basic" RISC pipeline and its also the basic pipeline breakdown used in current x86 CPUs.

 

[dmens]

sounds like the 5-stage MIPS2K from patterson.

in regards to that particular model, what you said is correct.

 

[Cooler]

dont forget if branch is misspredicted it must flush the pipes and then reload them.