Excellent article on Intels new transisters

[Phynaz]

If you're interested in learning about high-k insulaters and metal gates, this article is very informative.

IEEE article.

Edit:
Maybe this belongs in the highly techncal forum?

 

[Acanthus]

With how much Intel talks about this "breakthrough technology" it sure as hell doesnt seem to show up in the TDPs of Penryn. You would think an order of magnitude reduction in gate leakage would be enough for a noticable change. Even with Intels "lets cram as much cache as we can on our CPUs" philosophy.

 

[dmens]

1. leakage is only a fraction of the TDP number
2. the order of magnitude change is leakage compared to the old sio2 gate, all other factors held equal. that is not the case.

 

[Nemesis 1]

That was a great article . Very simply written so even I could understand it. Remarkable work at the atomic level. Doubling transitors and reducing heat and leakage . Wonderful work by Intel . This new 32nm transitor with new improved HighK and Gate

Has me Thinking 32nm will include 3D gates To improve source drain and leakage while possibly lowering drive current further. Or using same drive current for higher performance. If 3d gates will allow Intel to further shorten tube length . Nehalem C should hit really high frequencies.

I can't wait to see IBMs High k /metal gate silicon . Will it be Gate last like Intels or gate first. The traditional method.

 

[TuxDave]

Originally posted by: Nemesis 1
That was a great article . Very simply written so even I could understand it. Remarkable work at the atomic level. Doubling transitors and reducing heat and leakage . Wonderful work by Intel . This new 32nm transitor with new improved HighK and Gate

Has me Thinking 32nm will include 3D gates To improve source drain and leakage while possibly lowering drive current further. Or using same drive current for higher performance. If 3d gates will allow Intel to further shorten tube length . Nehalem C should hit really high frequencies.

I can't wait to see IBMs High k /metal gate silicon . Will it be Gate last like Intels or gate first. The traditional method.

Am I having reading comprehension problems or is there something missing...

 

[Phynaz]

Originally posted by: TuxDave

Originally posted by: Nemesis 1
That was a great article . Very simply written so even I could understand it. Remarkable work at the atomic level. Doubling transitors and reducing heat and leakage . Wonderful work by Intel . This new 32nm transitor with new improved HighK and Gate

Has me Thinking 32nm will include 3D gates To improve source drain and leakage while possibly lowering drive current further. Or using same drive current for higher performance. If 3d gates will allow Intel to further shorten tube length . Nehalem C should hit really high frequencies.

I can't wait to see IBMs High k /metal gate silicon . Will it be Gate last like Intels or gate first. The traditional method.

Am I having reading comprehension problems or is there something missing...

Read the article and it will all be clear.

Nemesis,
I'm betting it will be gate first. I think Intel will stand alone in changing not only what the transistor is made of, but how it's actually built.

 

[Phynaz]

Nevermind...

 

[Nemesis 1]

Originally posted by: Phynaz

Originally posted by: TuxDave

Originally posted by: Nemesis 1
That was a great article . Very simply written so even I could understand it. Remarkable work at the atomic level. Doubling transitors and reducing heat and leakage . Wonderful work by Intel . This new 32nm transitor with new improved HighK and Gate

Has me Thinking 32nm will include 3D gates To improve source drain and leakage while possibly lowering drive current further. Or using same drive current for higher performance. If 3d gates will allow Intel to further shorten tube length . Nehalem C should hit really high frequencies.

I can't wait to see IBMs High k /metal gate silicon . Will it be Gate last like Intels or gate first. The traditional method.

Am I having reading comprehension problems or is there something missing...

Read the article and it will all be clear.

Nemesis,
I'm betting it will be gate first. I think Intel will stand alone in changing not only what the transistor is made of, but how it's actually built.

I don't doubt what your saying to be fact . Never the less I am very intrigued by this concept. Can't wait to find out what side of the fence IBMs high k / metal gates fall on.
If IBM goes gate first and uses FinFet metal gates using the process discribed in the article. Than I will have to wait until Intels 32nm process using 3D gates last . To find out the true intrinsic value of gates first gates last in a truely unique concept in processor transistor tech.

 

[TuxDave]

Originally posted by: Phynaz

Originally posted by: TuxDave

Originally posted by: Nemesis 1
That was a great article . Very simply written so even I could understand it. Remarkable work at the atomic level. Doubling transitors and reducing heat and leakage . Wonderful work by Intel . This new 32nm transitor with new improved HighK and Gate

Has me Thinking 32nm will include 3D gates To improve source drain and leakage while possibly lowering drive current further. Or using same drive current for higher performance. If 3d gates will allow Intel to further shorten tube length . Nehalem C should hit really high frequencies.

I can't wait to see IBMs High k /metal gate silicon . Will it be Gate last like Intels or gate first. The traditional method.

Am I having reading comprehension problems or is there something missing...

Read the article and it will all be clear.

Nemesis,
I'm betting it will be gate first. I think Intel will stand alone in changing not only what the transistor is made of, but how it's actually built.

Ah, whether to deposit the gate before doping the source and drains. I'm not sure about the benefits of a 'gate last' fabrication but I can definitely tell you the problems. Gate first allow your source/drain dopants to naturally align to the gate since the gate is shielding the substrate. I can't imagine the alignment issues of doping the source drain with the separation and then trying to stick the gate in that gap. Yeesh, why do it the hard way?

 

[Nemesis 1]

Originally posted by: TuxDave

Originally posted by: Phynaz

Originally posted by: TuxDave

Originally posted by: Nemesis 1
That was a great article . Very simply written so even I could understand it. Remarkable work at the atomic level. Doubling transitors and reducing heat and leakage . Wonderful work by Intel . This new 32nm transitor with new improved HighK and Gate

Has me Thinking 32nm will include 3D gates To improve source drain and leakage while possibly lowering drive current further. Or using same drive current for higher performance. If 3d gates will allow Intel to further shorten tube length . Nehalem C should hit really high frequencies.

I can't wait to see IBMs High k /metal gate silicon . Will it be Gate last like Intels or gate first. The traditional method.

Am I having reading comprehension problems or is there something missing...

Read the article and it will all be clear.

Nemesis,
I'm betting it will be gate first. I think Intel will stand alone in changing not only what the transistor is made of, but how it's actually built.

Ah, whether to deposit the gate before doping the source and drains. I'm not sure about the benefits of a 'gate last' fabrication but I can definitely tell you the problems. Gate first allow your source/drain dopants to naturally align to the gate since the gate is shielding the substrate. I can't imagine the alignment issues of doping the source drain with the separation and then trying to stick the gate in that gap. Yeesh, why do it the hard way?

Another transistor process sequence, dubbed ?gate last,? circumvents the thermal annealing requirement by depositing the gate electrode materials after the source and drain are formed.] [IHowever, many of our peers saw the gate-last process, which we ultimately adopted, as too much of a departure and too challenging. [/i]Meanwhile, a third approach remarkable in its simplicity emerged. Called fully silicided gates, it lets you follow the normal gate-first process but then lets you turn the polysilicon gate into a metal-silicide gate, essentially replacing every other silicon atom with metal (usually nickel). Then, by doping the nickel silicide, you can alter its work function for use in either an NMOS device or a PMOS one. By late 2006, though, nearly everyone, including us, had given up on the fully ­silicided gates approach. [I]No one could move the silicide's work function quite close enough to where it needed to be. [/i]


Even tho Intel choose the challenging route the reason was because of the heat produced during the Annealing process.

As you can see the third approach even tho seemed remarkable in its simplicity turned out not so simple for intel as the second bold and undelined statement shows.


The old way of doing it is the first approach. The second approach was what Intel choose . So we know from this Intels gate material has low heat threshold. The third approach is were intel ran into alignment issues. So this is why intel choose gate last method.

 

[Acanthus]

Originally posted by: dmens
1. leakage is only a fraction of the TDP number
2. the order of magnitude change is leakage compared to the old sio2 gate, all other factors held equal. that is not the case.

You still expect a die shrink with very little revision to the architecture to reduce the tdp.

 

[Phynaz]

Originally posted by: Acanthus

Originally posted by: dmens
1. leakage is only a fraction of the TDP number
2. the order of magnitude change is leakage compared to the old sio2 gate, all other factors held equal. that is not the case.

You still expect a die shrink with very little revision to the architecture to reduce the tdp.

The days of automatic speed and power improvemets from process shrinks ended years ago.

 

[Acanthus]

Originally posted by: Phynaz

Originally posted by: Acanthus

Originally posted by: dmens
1. leakage is only a fraction of the TDP number
2. the order of magnitude change is leakage compared to the old sio2 gate, all other factors held equal. that is not the case.

You still expect a die shrink with very little revision to the architecture to reduce the tdp.

The days of automatic speed and power improvemets from process shrinks ended years ago.

Err 90nm => 65nm saw nice gains. That was a year ago.

If youre referring back to northwood vs prescott, there was a lot more than a process shrink going on.

 

[Phynaz]

Originally posted by: Acanthus

Originally posted by: Phynaz

Originally posted by: Acanthus

Originally posted by: dmens
1. leakage is only a fraction of the TDP number
2. the order of magnitude change is leakage compared to the old sio2 gate, all other factors held equal. that is not the case.

You still expect a die shrink with very little revision to the architecture to reduce the tdp.

The days of automatic speed and power improvemets from process shrinks ended years ago.

Err 90nm => 65nm saw nice gains. That was a year ago.

If youre referring back to northwood vs prescott, there was a lot more than a process shrink going on.

Then why are AMD's fastest chips 90nm? AMD got no gains going to 65nm. Prescott was not much more than a process shrink, and power went through the roof.

Like I said, it's over. Speed and power is all design now, not shrink. Did you read the article I linked?

 

[bryanW1995]

there has been a lot of hype surrounding the die shrink and other improvements for penryn. I for one will be disappointed if an "average" Q9450 doesn't oc 200-300mhz better than a G0 quad.

 

[Nemesis 1]

A penryn will O/C a lot more than a Conroe. @ XS Coolar hit 4.2 ghz stable on air with 4q early stepping of Penryn . Not the resale stepping.

 

[Acanthus]

Originally posted by: Phynaz

Originally posted by: Acanthus

Originally posted by: Phynaz

Originally posted by: Acanthus

Originally posted by: dmens
1. leakage is only a fraction of the TDP number
2. the order of magnitude change is leakage compared to the old sio2 gate, all other factors held equal. that is not the case.

You still expect a die shrink with very little revision to the architecture to reduce the tdp.

The days of automatic speed and power improvemets from process shrinks ended years ago.

Err 90nm => 65nm saw nice gains. That was a year ago.

If youre referring back to northwood vs prescott, there was a lot more than a process shrink going on.

Then why are AMD's fastest chips 90nm? AMD got no gains going to 65nm. Prescott was not much more than a process shrink, and power went through the roof.

Like I said, it's over. Speed and power is all design now, not shrink. Did you read the article I linked?

Ahh so theres no point to shrinks now, they just waste billions a year in research on it to cram more cache on the die.

AMD has been having trouble with 65nm for a very long time. Bad example.

 

[Phynaz]

Originally posted by: Acanthus

Originally posted by: Phynaz

Originally posted by: Acanthus

Originally posted by: Phynaz

Originally posted by: Acanthus

Originally posted by: dmens
1. leakage is only a fraction of the TDP number
2. the order of magnitude change is leakage compared to the old sio2 gate, all other factors held equal. that is not the case.

You still expect a die shrink with very little revision to the architecture to reduce the tdp.

The days of automatic speed and power improvemets from process shrinks ended years ago.

Err 90nm => 65nm saw nice gains. That was a year ago.

If youre referring back to northwood vs prescott, there was a lot more than a process shrink going on.

Then why are AMD's fastest chips 90nm? AMD got no gains going to 65nm. Prescott was not much more than a process shrink, and power went through the roof.

Like I said, it's over. Speed and power is all design now, not shrink. Did you read the article I linked?

Ahh so theres no point to shrinks now, they just waste billions a year in research on it to cram more cache on the die.

AMD has been having trouble with 65nm for a very long time. Bad example.

Please point out were I said there was no point to shrinks. The point of shrinks is to reduce manufacturung costs.

Anyway, since you refuse to read the linked aricle, I think were done here.

 

[TuxDave]

Originally posted by: Nemesis 1
Even tho Intel choose the challenging route the reason was because of the heat produced during the Annealing process.

As you can see the third approach even tho seemed remarkable in its simplicity turned out not so simple for intel as the second bold and undelined statement shows.

Hmm... it never occured to me that the gate wouldn't be able to survive the annealing process but I guess the gate material has changed significantly that it's possible. I wonder what effect it will have on analog transistors? Before with the gate first method, transistor's were subject to mismatch left to right due to shadowing when doping the source and drains. That's why for each matched transistor you had to split it into two which each being mirrored of each other. Makes me wonder if this is still an issue.

 

[Acanthus]

Originally posted by: Phynaz

Originally posted by: Acanthus

Originally posted by: Phynaz

Originally posted by: Acanthus

Originally posted by: Phynaz

Originally posted by: Acanthus

Originally posted by: dmens
1. leakage is only a fraction of the TDP number
2. the order of magnitude change is leakage compared to the old sio2 gate, all other factors held equal. that is not the case.

You still expect a die shrink with very little revision to the architecture to reduce the tdp.

The days of automatic speed and power improvemets from process shrinks ended years ago.

Err 90nm => 65nm saw nice gains. That was a year ago.

If youre referring back to northwood vs prescott, there was a lot more than a process shrink going on.

Then why are AMD's fastest chips 90nm? AMD got no gains going to 65nm. Prescott was not much more than a process shrink, and power went through the roof.

Like I said, it's over. Speed and power is all design now, not shrink. Did you read the article I linked?

Ahh so theres no point to shrinks now, they just waste billions a year in research on it to cram more cache on the die.

AMD has been having trouble with 65nm for a very long time. Bad example.

Please point out were I said there was no point to shrinks. The point of shrinks is to reduce manufacturung costs.

Anyway, since you refuse to read the linked aricle, I think were done here.

I have read every whitepaper and article on this matter, from their announcment of the new low-k material selection to this article that is linked. You must have me mistaken for someone who isnt a double major in electrical and materials engineering. 😉