[EuroGamer] AMD has developed a 20nm version of Xbox One APU

[f1sherman]

completely wrong. you have not understood how a node shrink works.

And now you are wrong. I have not understood how he thinks node shrink works because I was reinterpreting how I think he sees the shrink.
Later I understood what he means. He sees it as 1.9x times smaller chip with equal amount of transistors and 25% less power than the 28nm part.

And therefore his statement:

Note that 1.9x density shrinking with only 25% power scaling means that heat produced per unit area is going up.

Which again is ridiculous, because that would mean same size chip needs 1.9 x (100%-25%) ~ 150% power at same clock, effectively reducing maximum possible chip from 550-ish mm2 to 550/1.5 =366mm2

That statement on TSMC website is poorly worded. The density increase is not a OR choice. So you will get the density increase when you go for a node shrink.

Jesus Christ... not again. Where did I say you will not get a density increase regardless? It's uniform and compulsory 1.9x density increase that is nowhere implied by TSMC.
Check out AMD vs Nvidia tran. density increase, it's not the same - how come if TSMC claims uniform (this time around 1.9x) density increase?

 

[AtenRa]

In order to understand it better,

28nm Kabini
Die size = 105mm2
Speed = 1.6GHz
Power = 15W

20nm Kabini (direct shrink only) Two options

Option 1 (speed +30%)
Die size = ~55mm2
Speed = 1.6GHz + 30% = 2.08GHz
Power = 15W

Option 2 (Power _25%)
Die size = ~55mm2
Speed = 1.6GHz
Power = 15W - 25% = 11,25W

Hope that helps

 

[f1sherman]

What about 550mm2 R9 390x?

Bajillion watts due to power/area ~ 150% at the same clock?

 

[3DVagabond]

What about 550mm2 R9 390x?

Bajillion watts due to power/area ~ 150% at the same clock?

We have no idea because we don't know the chips power characteristics.

 

[f1sherman]

GPU Tran(M) die size(mm2) density 1/M
7350 292 59 4.95
7450 370 67 5.52
7510 716 118 6.07
(40nm)

7770 1500 123 12.195
7790 2080 160 13
7870 2800 212 13.21
7970 4313 352 12.25
290X 6200 438 14.155
(28nm)

So much about uniform density on the same process.

 

[AtenRa]

What about 550mm2 R9 390x?

Bajillion watts due to power/area ~ 150% at the same clock?

I can tell you what a 20nm direct shrink of 28nm Hawaii could be,

28nm R9 290X
Die size = 438mm2
Transistor Count = ~6B
Speed = 1000MHz
Power = 250W

20nm R9 290X
Die size = ~230mm2
Transistor Count = ~6B
Speed = 1000MHz
Power = 187W

Or you could raise speed to 1300MHz at 250W.

At 20nm, you can also have a ~438mm2 die with ~11,4B transistors at 1300MHz 1000MHz and 250W. That is almost double the tranistor count at same power with higher speed as 28nm Hawaii.

For a 20nm 550mm2 die, it could have ~14,3B transistors at ~1000MHz ~250W

But all that by simple using the same architecture of Hawaii.

Edit: 1000MHz with double the transistor count

 

[AtenRa]

GPU Tran(M) die size(mm2) density 1/M
7350 292 59 4.95
7450 370 67 5.52
7510 716 118 6.07
(40nm)

7770 1500 123 12.195
7790 2080 160 13
7870 2800 212 13.21
7970 4313 352 12.25
290X 6200 438 14.155
(28nm)

So much about uniform density on the same process.

You comparing different architectures. Try comparing a direct shrink of each GPU to a lower node.

 

[f1sherman]

I can tell you what a 20nm direct shrink of 28nm Hawaii could be,

28nm R9 290X
Die size = 438mm2
Transistor Count = ~6B
Speed = 1000MHz
Power = 250W

20nm R9 290X
Die size = ~230mm2
Transistor Count = ~6B
Speed = 1000MHz
Power = 187W

Or you could raise speed to 1300MHz at 250W.

yes, this is all OK

230mm2, ~6B tran, 1300MHz, 250W

At 20nm, you can also have a ~438mm2 die with ~11,4B transistors at 1300MHz and 250W. That is almost double the tranistor count at same power with higher speed as 28nm Hawaii.

For a 20nm 550mm2 die, it could have ~14,3B transistors at ~1000MHz ~250W

438mm2, ~11.4B, 1300MHz, 250W???

Uhm... hell no! All of that is wrong

 

[AtenRa]

438mm2, ~11.4B, 1300MHz, 250W???

Uhm... hell no! All of that is wrong

At 20nm you have 1.9X density, it will get you ~11,4B transistors at the same die size of 438mm2.

You also get 30% higher speed at same power of 28nm.

 

[f1sherman]

At 20nm you have 1.9X density, it will get you ~11,4B transistors at the same die size of 438mm2.

You also get 30% higher speed at same power of 28nm.

So you are keeping the same chip size, right? That is how I originally understood it when re-interpreting Enigmoid
But you guys were actually insisting on the same tran count (direct shrink).

You need to make up your mind. Cant have both.

20nm R9 290X
Die size = ~230mm2
Transistor Count = ~6B
Speed = 1000MHz
Power = 187W

Or you could raise speed to 1300MHz at 250W

At 20nm, you can also have a ~438mm2 die with ~11,4B transistors at 1300MHz and 250W.

 

[ShintaiDK]

It needs to be the same transistor count yes.

So exact same chip shrinked. Then you get smaller size and one of the 2 properties with speed or power reduction.

However, it doesnt always work that way in reality. Because the electrical properties of the designs and physical limits are in place.

Else we would have 20Ghz+ CPUs today for example.

 

[f1sherman]

Agreed ^^

 

[AtenRa]

So you are keeping the same chip size, right? That is how I originally understood it when re-interpreting Enigmoid
But you guys were actually insisting on the same tran count (direct shrink).

You need to make up your mind. Cant have both.

You can have a direct shrink of 6B transistors down to ~230mm2

OR

438mm2 at 11.4B transistors

I believe it was clear what i said.

 

[f1sherman]

You can have a direct shrink of 6B transistors down to ~230mm2

OR

438mm2 at 11.4B transistors

I believe it was clear what i said.

250W that you attributed to both options is the problem here

 

[ShintaiDK]

You can have a direct shrink of 6B transistors down to ~230mm2

OR

438mm2 at 11.4B transistors

I believe it was clear what i said.

What you said was wrong.

You said twice the transitors on your 290X example and 30% higher speed on top. And we all know that wouldnt happen. Just as it didnt happen before due to design limitations.

Also you cant use the power saving directly either.

All the shrink numbers are on per transistor basis. And not in relation to any design.

 

[AtenRa]

250W that you attributed to both options is the problem here

Read again what i said,

I can tell you what a 20nm direct shrink of 28nm Hawaii could be,

28nm R9 290X
Die size = 438mm2
Transistor Count = ~6B
Speed = 1000MHz
Power = 250W

20nm R9 290X
Die size = ~230mm2
Transistor Count = ~6B
Speed = 1000MHz
Power = 187W

Or you could raise speed to 1300MHz at 250W.

At 20nm, you can also have a ~438mm2 die with ~11,4B transistors at 1300MHz and 250W. That is almost double the tranistor count at same power with higher speed as 28nm Hawaii.

For a 20nm 550mm2 die, it could have ~14,3B transistors at ~1000MHz ~250W

But all that by simple using the same architecture of Hawaii.

With a direct shrink you only have 250W if you raise the speed by 30%.

For the same die size you get 11,4B transistors (1.9x) and keeping the same speed your power stays at 250W as well.

 

[f1sherman]

But I understood you well.
It's just that - where do you get that last part from? This:

For the same die size you get 11,4B transistors (1.9x) and keeping the same speed your power stays at 250W as well.

You keep interchanging same tran count and same size at the same power budget and the same speed.

And you get 250W for 230mm2, 6B, 1300MHz Hawaii (direct shrink) and for 438mm2, 11.4B, 1300MHz (upscaled Hawaii)

 

[AtenRa]

What you said was wrong.

You said twice the transitors on your 290X example and 30% higher speed on top. And we all know that wouldnt happen. Just as it didnt happen before due to design limitations.

Also you cant use the power saving directly either.

All the shrink numbers are on per transistor basis. And not in relation to any design.

Ahh yes,

this had to be double the transistors with 1000MHz at 250W.

 

[ShintaiDK]

Ahh yes,

this had to be double the transistors with 1000MHz at 250W.

Thats very unlikely to happen. Again, twice the transistors gives a completely new design and new issues. And its very unlikely you get what you write.

It may end up as a 350W chip at 1000Mhz.

 

[AtenRa]

ok guys I fixed that

 

[f1sherman]

OK good day to you all. Gotta go

 

[SPBHM]

hopefully it will give them enough power savings to build a much smaller and simpler console, and help to cut costs and allow them to target a significantly lower price than the PS4, because the sales figures for the Xb1 are disappointing compared to the PS4, and I think making it significantly cheaper than the PS4 is something they have to do.

as for performance/clock, they would never target higher performance with a die shrink like this, it would only cause problems, it's all about lowering the cost

 

[ShintaiDK]

hopefully it will give them enough power savings to build a much smaller and simpler console, and help to cut costs and allow them to target a significantly lower price than the PS4, because the sales figures for the Xb1 are disappointing compared to the PS4, and I think making it significantly cheaper than the PS4 is something they have to do.

as for performance/clock, they would never target higher performance with a die shrink like this, it would only cause problems, it's all about lowering the cost

Smaller and simpler yes.

Cut cost (BOM wise)? Very unlikely. The main savings would be logistics/RMA.

When you look on the BOM for both consoles. The APU part only account for around 25% of the total cost. For the PS4 the GDDR cost is almost as high as the APU. The easiest way for cost savings on these consoles may simply be newer node for DDR/GDDR production. Also the APU itself is unlikely to get lower cost due to the node change.

 

[SPBHM]

Smaller and simpler yes.

Cut cost (BOM wise)? Very unlikely. The main savings would be logistics/RMA.

When you look on the BOM for both consoles. The APU part only account for around 25% of the total cost. For the PS4 the GDDR cost is almost as high as the APU. The easiest way for cost savings on these consoles may simply be newer node for DDR/GDDR production. Also the APU itself is unlikely to get lower cost due to the node change.

well, I was also thinking about the other power related costs, like the power supply and cooling

 

[AtenRa]

Smaller and simpler yes.

Cut cost (BOM wise)? Very unlikely. The main savings would be logistics/RMA.

When you look on the BOM for both consoles. The APU part only account for around 25% of the total cost. For the PS4 the GDDR cost is almost as high as the APU. The easiest way for cost savings on these consoles may simply be newer node for DDR/GDDR production. Also the APU itself is unlikely to get lower cost due to the node change.

That is only in the beginning, APU cost will go down as 20nm will get depreciated over time and wafer price will decrease.