EE Homework Help

[agnitrate]

I am taking an Intro to Digital Circuits class and I swear it's the most unorganized class ever. The book has problems only at the end of each chapter and it's not divided into sections, so I have no concrete solutions to work with. To top it off, the examples given in class are nothing like the ones we are getting for our homework.

I need help (so far) on the first problem here.

for a) I calculated the resistance as being the V(output low max) / I = .2 V / 1 mA = 200 Ohms. I believe this is the correct answer.

b) I'm not sure how to relate the .4 mA of current needed by the 7404 inverter to this problem. Does the resistor need to prove a total current of (1 mA + .4 mA ) so 1 mA sinks via the 74HC03 and .4 mA is given to the inverter? If so, I would imagine that the resistance would be (5V - .2V) / (1 mA + .4 mA) = 3428 Ohms, but this seems awfully high.

Am I missing something on b)?

c) I cannot complete until I get the proper resistance for B.

Yeah, I know homework threads suck, but this isn't due until Friday and I want to get started on it and try to actually understand these concepts that the class keeps breezing over.

Thanks for any help that can be offered.

-silver

 

[agnitrate]

bump for the Tuesday crowd

 

[rival]

no clue, way over my head, i only do simple ac/dc circuits

 

[amoeba]

Ok, I'll give some help here. Although the question is worded quite badly and why you would mix cmos circuitry with a resistor, I don't know.

So, the first clue should be that its a CMOS nand. So CMOS has full voltage swings which means that normally without that resistor there, the VoL ( voltage output low) should be 0v.

But because there is that resistor there, the output voltage is .2v instead.

Thus, the voltage at the node connected to the nand output, at the lower end of the resistor is .2 while the top end is connected with vdd=5v. Thus I believe for part B,
4.8 volts are dissipated over the resistor.

Now here comes the tricky part, I'm not sure what sinking the current means. Specifically where is the 1mA current. It could be that there is a 1 mA current from the output node of the nand to the drain/source of the nand. and .4 mA from the input of the inverter to that same node. Thus using KCL, you could infer .6mA through the resistor.
Or it could mean 1mA through resistor. The wording is not clear. so then you can take the 4.8V you just calculated, and divide by the current. My guess is the current is .6mA. which would give you 8kohm for the resistor.

Then you would use a tplh equation for part c. Although it says estimate, so you can just use rc constant circuit delay. Model the inverter as a capacitor.

 

[sciencewhiz]

are you sure that this isn't violating the thing you sign on the first page?

 

[LordSnailz]

agnitrate: I think what you have is correct, I agree with amoeba, the wording is a bit confusing. Pls. come back when the solution are handed out, but I think what you've said on your original post is correct.

 

[agnitrate]

Originally posted by: amoeba


Now here comes the tricky part, I'm not sure what sinking the current means. Specifically where is the 1mA current. It could be that there is a 1 mA current from the output node of the nand to the drain/source of the nand. and .4 mA from the input of the inverter to that same node. Thus using KCL, you could infer .6mA through the resistor.
Or it could mean 1mA through resistor. The wording is not clear. so then you can take the 4.8V you just calculated, and divide by the current. My guess is the current is .6mA. which would give you 8kohm for the resistor.

Then you would use a tplh equation for part c. Although it says estimate, so you can just use rc constant circuit delay. Model the inverter as a capacitor.

Ah! That makes sense now that I think about it. Sinking the current we defined as the current is going from Vdd->load->into the gate whereas sourcing current is Vdd->gate->load. You explained it much better than I could think of it. That does make sense. There's initally 5v sitting on the resistor but it gets knocked down to .2v at the output. So we know the voltage drop is 4.8v. If the inverter needs .4mA of current and my output is currently sinking 1 mA, it makes sense that there is .6 mA of load on the resistor. So we get V/I = R = 4.8 / .0006 = 8000 Ohms as you stated.

I thought this seemed awfully high but there is a problem in the book which is a similar situation but not quite the same that needs a 43.3 kOhm resistor :shocked; I computed the RC time const. for this and it seemed pretty slow, but I guess it would be w/ 8000 Ohms. Most of the other CMOS circuits have a rise time of about 10-20 ns and fall of 10 ns. My beast is over 100 ns.

Thanks for the help and I might have to update later with questions for the other problems for you smart people

sciencewhiz, I don't believe this violates my agreement because I am doing the work and am not blindly asking somebody for the answers. I refuse to be given answers. I want to know why this stuff works and for what reasons. It drives me crazy that this course isn't doing that and we just seemingly memorize formulas and techniques. Surely not what I expected for a EE course, even though it is only an introduction.

Thanks again guys!

-silver