Originally posted by: LTC8K6
Yeah, just going to 4 cpus would probably cause the new Xeons to stumble again against the Opterons.
Originally posted by: Jeff7181
Originally posted by: LTC8K6
Yeah, just going to 4 cpus would probably cause the new Xeons to stumble again against the Opterons.
At least until Intel makes either dual chipsets, or a chipset with dual memory controllers.
Can you say Obliterate ?Originally posted by: ribbon13
I wonder how a Quad dual-core Opteron would fair against a Intel with it's limited memory bandwidth?
Originally posted by: Jeff7181
Originally posted by: clarkey01
LTC8K6 would you elaborate on your thougts, I get the feeling your hinting that Xeons are faster then Opterons all around, and lol im not going to argue but would you add to that or back it up, hey,just for fun
Well as mentioned, the current Xeons are Prescott based. Because of the design, performance is extremely dependant on keeping the pipeline full, which lots of memory bandwidth helps to achieve. By memory, I don't just mean system RAM... I mean L2 cache, L1 cache, and actual registers. Too slow, or too little memory will create pipeline stalls that effect CPU's with long pipelines much more than CPU's with short pipelines. So increasing the number and to some extent, the size of registers (the fastest form of memory as far as the CPU is concerned) reduces the dependency on the L1 cache, and the L2 cache, and system RAM. So it makes sense that a design that is MORE dependant on these things to perform well will benefit more by improving these things... doesn't it?
Originally posted by: clarkey01
Originally posted by: Jeff7181
Originally posted by: clarkey01
LTC8K6 would you elaborate on your thougts, I get the feeling your hinting that Xeons are faster then Opterons all around, and lol im not going to argue but would you add to that or back it up, hey,just for fun
Well as mentioned, the current Xeons are Prescott based. Because of the design, performance is extremely dependant on keeping the pipeline full, which lots of memory bandwidth helps to achieve. By memory, I don't just mean system RAM... I mean L2 cache, L1 cache, and actual registers. Too slow, or too little memory will create pipeline stalls that effect CPU's with long pipelines much more than CPU's with short pipelines. So increasing the number and to some extent, the size of registers (the fastest form of memory as far as the CPU is concerned) reduces the dependency on the L1 cache, and the L2 cache, and system RAM. So it makes sense that a design that is MORE dependant on these things to perform well will benefit more by improving these things... doesn't it?
Thats all great, why did you quote me ?
Originally posted by: Avalon
Originally posted by: clarkey01
Originally posted by: Jeff7181
Originally posted by: clarkey01
LTC8K6 would you elaborate on your thougts, I get the feeling your hinting that Xeons are faster then Opterons all around, and lol im not going to argue but would you add to that or back it up, hey,just for fun
Well as mentioned, the current Xeons are Prescott based. Because of the design, performance is extremely dependant on keeping the pipeline full, which lots of memory bandwidth helps to achieve. By memory, I don't just mean system RAM... I mean L2 cache, L1 cache, and actual registers. Too slow, or too little memory will create pipeline stalls that effect CPU's with long pipelines much more than CPU's with short pipelines. So increasing the number and to some extent, the size of registers (the fastest form of memory as far as the CPU is concerned) reduces the dependency on the L1 cache, and the L2 cache, and system RAM. So it makes sense that a design that is MORE dependant on these things to perform well will benefit more by improving these things... doesn't it?
Thats all great, why did you quote me ?
Because he was responding to you?![]()
Originally posted by: clarkey01
Originally posted by: Avalon
Originally posted by: clarkey01
Originally posted by: Jeff7181
Originally posted by: clarkey01
LTC8K6 would you elaborate on your thougts, I get the feeling your hinting that Xeons are faster then Opterons all around, and lol im not going to argue but would you add to that or back it up, hey,just for fun
Well as mentioned, the current Xeons are Prescott based. Because of the design, performance is extremely dependant on keeping the pipeline full, which lots of memory bandwidth helps to achieve. By memory, I don't just mean system RAM... I mean L2 cache, L1 cache, and actual registers. Too slow, or too little memory will create pipeline stalls that effect CPU's with long pipelines much more than CPU's with short pipelines. So increasing the number and to some extent, the size of registers (the fastest form of memory as far as the CPU is concerned) reduces the dependency on the L1 cache, and the L2 cache, and system RAM. So it makes sense that a design that is MORE dependant on these things to perform well will benefit more by improving these things... doesn't it?
Thats all great, why did you quote me ?
Because he was responding to you?![]()
Didnt asnwer my question
Originally posted by: clarkey01
My thought was that opteron was always the more rounded chip , from LTC8K6 post he hinted that the chip was now more dominant and therefore a better choice over opteron, I just ask if this was the case.
How come the new Opteron is getting is ass kicked most of the time by the new Xeon?
I didn't think the extra cache and the faster bus could make such a difference.
I guess more than 2 CPU's might make a difference, though.
Originally posted by: clarkey01
Originally posted by: clarkey01
My thought was that opteron was always the more rounded chip , from LTC8K6 post he hinted that the chip was now more dominant and therefore a better choice over opteron, I just ask if this was the case.
That question
Yes, it more-or-less does, usually the memory controller has to be designed to support either/both (I think - I would assume that it would have to delay some of the timings by one clock-tick to deal with interfacing with the registers on the DIMM boards.)Originally posted by: Gamingphreek
However:
Link
Abit i guess thinks there is a difference between the two.
Also why would the boards make it any different... doesn't this have to do with the Memory Controller?
-Kevin
Originally posted by: Gamingphreek
However:
Link
Abit i guess thinks there is a difference between the two.
Also why would the boards make it any different... doesn't this have to do with the Memory Controller?
-Kevin
Yahoo, for instance, has come back three times to buy Sun Fire V20z servers to support some of its workloads. Yahoo benchmarked those applications on Xeon-based systems using the 64-bit "Nocona" processors from Intel against the V20z servers, and found that it needed 660 Xeon servers to support the workload. The same workload could run on 460 Opteron servers and deliver the same performance, which is a significant savings in money. And each V20z server burned quite a bit less electricity and dissipated a bit less heat, so the heat profile of the Opteron solution was significantly lower than the Xeon solution. A similar benchmark by the University of Leicester in the United Kingdom required 750 Xeon servers to do the work of 500 Opteron servers, he said.
That makes sense. It seems doubtful the power&heat of the new Nocona is any better than the last, and that combined with the added expense of keeping the ambient room temp the same would make the cost of even the same number higher correct?Originally posted by: LTC8K6
That article doesn't say whether the comparison was with the considerably faster 2MB L2 cache Noconas, though.
It probably wasn't, since they are just coming out.