Dual Core 65nm Preview at Tom's HG

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stevty2889

Diamond Member
Dec 13, 2003
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They are still seperate die, just like smithfield, it's 2 cedar mill die slapped together in one package, so each chip only has 2mb of cache.
 

Viditor

Diamond Member
Oct 25, 1999
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Originally posted by: stevty2889
They are still seperate die, just like smithfield, it's 2 cedar mill die slapped together in one package, so each chip only has 2mb of cache.

True...but the net cost of each CPU will still be quite high (though you're right in that glueing 2 together allows for an easier ramp and binning).
 

Accord99

Platinum Member
Jul 2, 2001
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Originally posted by: Viditor
Originally posted by: stevty2889
I don't think they will cost much more. The cache is larger, but the die size is smaller due to the 65nm proccess, so it doesn't really cost more to produce the chips, other than the cost of the new proccess.

True, but remember that 1MB of cache is about 40-50% larger than the core...these will have a total of 4MB cache.

On Prescott, the 1MB L2 cache is roughly 30% of the core. The addition of the second MB of cache roughly increased the die size ~25% to around 135mm^2.

http://techreport.com/reviews/2005q1/pentium4-600/index.x?pg=1

Cache is also a lot cheaper than logic, as defects aren't fatal and can be worked around with redundancies or selling them as Celerons.
 

coldpower27

Golden Member
Jul 18, 2004
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Originally posted by: Viditor
Originally posted by: Duvie
I always though cache was expenisve and added to heat...What a waste if this is the type of gains it got ....256 to 512 was big and even 512 to 1mb was nice...however 1mb to 2mb was anemic and the 2mb to 4mb seem like more unused potential...

I imagine there are some apps like superpi and other that may like this...the question is is this the same 6xx series cache??? You know the cache that was slower then the 5xx series cache with its increased latency...

Cache is VERY expensive (it adds more to the die size than the core by about 2 to 1), but doesn't necessarily add more heat...by adding cache, you may increase the aggregate heat, but you decrease the number of localized "hot spots" on the die.

One thing to note, the new Intel dual cores (900 series) will almost certainly be more expensive than their 800 series brethren...

Intel's actually excellent with cache, so it doesn't really add all that much to the core, on the 65nm node the structuring of this 2x2MB of cache should be at most 45-50% of the die surface area. Similar to the configuration of Prescott 2M, bear in mind though for AMD, 1MB cach on the Clawhammer/San Diego represents mroe then half the die area. But with the 65nm process die size is likely in the Manchester core size range.
 

Furen

Golden Member
Oct 21, 2004
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A few things to point out: 2.8GHz is the lowest a Prescott CPU can clock using a FSB speed of 200MHz (800 QDR) since its lowest multiplier is 14, this seems to be a limitation that is shared by cedarmill/presler, so they cannot lower the clock to less than 2.8ghz using speedstep. Intel's ultradense SRAM (as in cache) has a much higher latency penalty, but this is offset by the operating clockspeed (the latency is in clock cycles, after all). That is the reason why Pentium Ms do not use that high-density SRAM. These 65nm shrinks are a huge improvement over the 90nm parts (yes, huge) but, unfortunately, will not lead to much higher clock speeds, since current leakage seems to be pretty high anyway. 65nm parts will use less silicon, but that does not mean they will be cheaper to produce. Intel has to amortize its transition and R&D expenses on all the 65nm parts and still make a profit, which should make the price a bit higher than current 90nm chips.
 

coldpower27

Golden Member
Jul 18, 2004
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Originally posted by: Furen
A few things to point out: 2.8GHz is the lowest a Prescott CPU can clock using a FSB speed of 200MHz (800 QDR) since its lowest multiplier is 14, this seems to be a limitation that is shared by cedarmill/presler, so they cannot lower the clock to less than 2.8ghz using speedstep. Intel's ultradense SRAM (as in cache) has a much higher latency penalty, but this is offset by the operating clockspeed (the latency is in clock cycles, after all). That is the reason why Pentium Ms do not use that high-density SRAM. These 65nm shrinks are a huge improvement over the 90nm parts (yes, huge) but, unfortunately, will not lead to much higher clock speeds, since current leakage seems to be pretty high anyway. 65nm parts will use less silicon, but that does not mean they will be cheaper to produce. Intel has to amortize its transition and R&D expenses on all the 65nm parts and still make a profit, which should make the price a bit higher than current 90nm chips.

The cache on Dothan is still a fairly dense animal. Even assuming the cache represents 65% die area, which is 54.3 mm2 out of 83.6mm2, this is still better then the cache on San Diego 50% (conservative estimate) 57.5mm2 out of 115mm2. You have 2MB on Dothan in ~ same room as 1MB on San Diego, and Dothan cache is quicker. It's slightly less dense then the stuff in Prescott-2M but only slightly less so. And as you are aware both cores on the 90nm node.

What you are talking, about is recoupment of R&D costs of development of the 65nm process which to be fair is spread out over the life of the process itself. This would be analagous to AMD not making ANY money on 90nm parts at their introduction, due to the need to recoup costs on development of the 90nm process. Process transitions take time and do ensure higher profitability in the long run as you can produce more processors per wafer.


 

Furen

Golden Member
Oct 21, 2004
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Sorry, sorry, I did not mean amortize. I meant that they will sell them for a premium in order to show short-term returns on a long-term investment. Chips on new processes normally have a premium, regardless of the fact that the new process will give them good return on investment over its lifetime simply because: a) it's easy to charge a premium on chips that are more efficient, faster and better, overall; and b) investors love seeing returns on investments, which, in turn, makes everyone (or rather everyone that matters to Intel's management) richer.

Now, this does not mean that they will actually be sold at a premium (since there are rumors that they wont) but they wont necessarily be cheaper as the fact that their dies will be smaller (much smaller, by the way, since the cache on Prescott2Ms is about 50% of the die size--to err on the side of caution--and these will ONLY get more cache, the rest of the die will remain the same) would suggest, which would lessen the price ramp-down that tech items normally have. AMD did do this when it went to 90nm... remember those super expensive winchesters? They were socket 939 but they were more expensive than comparable socket 754 newcastles, and their die size was much smaller (since AMD didnt add more cache, etc). Higher-than-normal margins on new process chips help offset any transitional, short-term expenses that may be incurred.
 

coldpower27

Golden Member
Jul 18, 2004
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Originally posted by: Furen
Sorry, sorry, I did not mean amortize. I meant that they will sell them for a premium in order to show short-term returns on a long-term investment. Chips on new processes normally have a premium, regardless of the fact that the new process will give them good return on investment over its lifetime simply because: a) it's easy to charge a premium on chips that are more efficient, faster and better, overall; and b) investors love seeing returns on investments, which, in turn, makes everyone (or rather everyone that matters to Intel's management) richer.

Now, this does not mean that they will actually be sold at a premium (since there are rumors that they wont) but they wont necessarily be cheaper as the fact that their dies will be smaller (much smaller, by the way, since the cache on Prescott2Ms is about 50% of the die size--to err on the side of caution--and these will ONLY get more cache, the rest of the die will remain the same) would suggest, which would lessen the price ramp-down that tech items normally have. AMD did do this when it went to 90nm... remember those super expensive winchesters? They were socket 939 but they were more expensive than comparable socket 754 newcastles, and their die size was much smaller (since AMD didnt add more cache, etc). Higher-than-normal margins on new process chips help offset any transitional, short-term expenses that may be incurred.

Well 2x2MB on Presler is just basically two Prescott-2M's on the 65nm process AKA Cedar Mill on a single package, so 45-50% of the die will remain the overall cache amount on the chip as you now have two cores instead of one, vs the probable 25% or something for the existing Smithfield based Pentium D. What I am getting at is this will be cheaper for Intel to produce, with the reduced die size, and the premium associated with new technology is normal, but that would be in favor of Intel as they would just get more money from it. So I am saying it will be cheaper for Intel, but it would probably cost us the same or more which I don't have a problem with.

I also wouldn't call comparing the S939 Winchesters, a fair comparison to the 130nm Newcstles on S754. At that time prior to the 90nm process there weren't any 3000+ or 3200+ on the S939, so there wasn't an older directly comparable substitute. AMD was also beginning by that time to move S754 towards a more value oriented platform. The premium came from the fact that there weren't any exisiting S939 parts at those speed grades to begin with, so it already had a large market demand, that hadn't been priorly satisfied yet. The 3500+ though did have the older counter part, and the price differences should of been noticable but not overwhelming for that part.

We will have to see how Intel prices their cores, but for Cedar Mill it seems, it's more likely they will price them at parity since they are a straight optical shrink.

For Presler, we should expect a price premium due to them being a higher level product AKA Pentium D9xx Series over existing Smithfield processors.

It all depends, with Prescott they had price parity with Northwood at launch and not too long after lower then Northwood, due to the cessation of production of those processors/continued demand with decreased supply.