I disagree. I think it does hinder it, but it just has more resources thrown at it, and tends to be on a better process technology, and is always being pushed hard for time-to-market.
The P4 has many innovative technologies (some of which actually hinder performance on current code which is unoptimized for the architecture, and I'm talking about more than just SSE2 and FPU stuff). Imagine if RISC vendors used them all at the same time that Intel has been - the RISC boxes would probably smash x86. The PA-RISC 8700, to quote Paul DeMone, is "HP?s third and most recent attempt to hide a superscalar RISC CPU in an SRAM." It's a standard 4-issue RISC chip, with some cool features, but mostly, mammoth on-die caches. If other architectures included as many innovations as the P4 does, x86 would be in trouble. Thankfully, most other vendors have smaller development teams, use older process technologies, and are more likely to be hampered by politics.