Does the P4 still have a "Double-Pumped" MPU?

[Lazn]

If you remember, the Williamette when it was introduced was touting it's "Double-Pumped" MPU that ran at twice the clock speed of the rest of the CPU.

http://www.eetimes.com/semi/ne...tml?articleID=18303579
"Willamette's arithmetic logic unit (ALU) is double-pumped, running at twice the chip's clock frequency."

Is this true of current P4 designs? If so, the MPU of a 3.8Ghz Prescott would be running 7.6 Ghz!!

Or did Intel change their design with the Northwood and later processors and drop this?

Just curios.

==>Lazn

 

[TuxDave]

I believe they are still double pumped. It's pretty insane.

 

[sao123]

The last review of a Pentium 4 I read was for the P4 @ 3.0 Ghz on the I875Chipset.
It still had listed the ALU as "Rapid Execution Engine - ALU clocked at 2X frequency of core."
Even with prescott there has not that big of a revamping of Netburst. So I believe that is still true.

You can read more about the Willamette ALU 2x Here.
(If the page redirects you to the first page of the article... Its page 5)

 

[Lazn]

That is what I thought, but was not sure.

Rather amazing really.

==>Lazn

 

[TuxDave]

Yeah, the can make some real scraming ALUs with their transistors. I attended a talk by their engineers and from what I saw, they use some very non-standard topologies in adders.

 

[CTho9305]

This is a pretty cool writeup on the technology in the 90nm Prescott (it's many pages long, and for some reason loads orders of magnitude faster in MSIE than Mozilla 😕 - Intel must be doing something funny). Note that Tejas was not using this logic style.

 

[JarredWalton]

[Take with a BIG grain of salt...]

I seem to recall hearing or reading something at one point that said the Prescott had tweaked the "Rapid Execution Units" so that they were no longer 2X core clock speed. Instead, they were some odd ratio like 1.5X core clock speed. Of course, it's not that they actually run faster, but that they can grab two simple INT instructions on each clock cycle. So with the change (if it happened), they could only grab two instructions every-other cycle or something weird. Unfortunately, I can't find any relevant link for this right now, and I may simply be hallucinating. 🙂

 

[BEL6772]

Here is another Intel write-up. This one deals with the Rapid Execution Engine in a little more detail. Basically, Prescott still has two integer ALUs that run at 2x core clock, but there are other execution units within the Rapid Execution Engine that run at 1x clock. Overall the Rapid Execution Engine can execute up to six micro-ops per clock cycle.