- Jul 4, 2000
- 8,867
- 51
- 91
With the multiplier locked on an Intel cpu this does not look good????
The P4 has a 100 MHz front-size bus that uses quad-pumped data (effectively QDR) to move 3.2 GBytes per second to the processor. Similar to the Athlon 100 MHz DDR FSB that is effectively 200 MHz of data, the P4's FSB transfers data at an incredible 400 MHz. As a side note, this does not bode well for overclockers. We saw a hard limit of about 110 MHz with the Athlon designs, which was pretty tough to get by. The increased precision required for DDR and QDR data transfers means that overclocking may be quite limited as clock signals become increasingly messy as they run farther out of spec. The 3.2 GB throughput is the same as the peak transfer rate of the dual Direct Rambus DRAM subsystem. It will be interesting to see if DRAM performs better with a CPU architecture it is designed for from the ground up.
This came from Game PC
The P4 has a 100 MHz front-size bus that uses quad-pumped data (effectively QDR) to move 3.2 GBytes per second to the processor. Similar to the Athlon 100 MHz DDR FSB that is effectively 200 MHz of data, the P4's FSB transfers data at an incredible 400 MHz. As a side note, this does not bode well for overclockers. We saw a hard limit of about 110 MHz with the Athlon designs, which was pretty tough to get by. The increased precision required for DDR and QDR data transfers means that overclocking may be quite limited as clock signals become increasingly messy as they run farther out of spec. The 3.2 GB throughput is the same as the peak transfer rate of the dual Direct Rambus DRAM subsystem. It will be interesting to see if DRAM performs better with a CPU architecture it is designed for from the ground up.
This came from Game PC