The larger size of the cell improves the performance since it has a higher cell capacitance – more electrons can be stored, and a better natural Vt distribution (~50%) is achieved. (Note that at 20-nm planar, less than 10 electrons gave 100mv Vt shift!)
Number of electrons/100mV Vt shift (left), and Vt distribution vs 20-nm planar flash (Source: Intel/Micron/IEDM)
The cell geometry also means that the cell/cell interference is reduced – again, comparing to the 20-nm planar chip;
Cell/cell interference of 3D-NAND vs planar NAND (Source: Intel/Micron/IEDM)
We will see what the commercial part looks like when we get our hands on one, likely in the first few months of next year. Unfortunately there are no scale bars on any of the images, so we have no feel for what the actual dimensions are; though probably not too different from the Samsung, which is classed as a 40-nm device.