Originally posted by: bgeh
Originally posted by: mngisdood
IIRC the higher bandwidths are more benefitial to P4 processors (esp. p4c) than to AXP's. I'll try to dig up some numbers...
i agree, for the p4 architecture, higher bandwidths are more beneficial, while for the Athlon XP's, lower latencies are better
I too agree. As demonstrated at Aceshardware (not to mention Anands

)A lack of internal bitwidth is bottlenecking the Athlon. Just as the P6 Pentium core began to run out of steam at the end of it's architecural life-cycle, so to has the Athlon been running out of the headroom that existed at lower FSB and RAM speeds. There were a pair of nice articles that are easy to read
detailing just this scenario and also
here. They are rather old, and yet so prophetic it would make any microprocessor student take note (i sure did). Can't wait to see how this theory plays out with Athlon/Opteron's onboard DRAM controller. It ought to be
very interesting.
People automatically assume more is better, which is correct. More is better. End of story. There is no down side to having more RAM bandwidth.
Terry, I agree that we all love more RAM bandwidth, but there
IS a downside. When the
saturation point is reached on
any bus or interconnect, whether it be fsb, PCI, internal cache-to-execution-pipeline(bitwidth) or even Gbit LAN, we see a ratio of diminishing returns. As that saturation point is neared, the
COST of producing silcon and interconnects (buses) able to handle those higher frequencies becomes increasingly less beneficial because the
performance ratio is diminishing.
Think of it as having a huge enigine in a car being fed by too small fuel lines. Starvation is occuring. This is exactly what happened when the Pentium4 was first released. The only difference was that most of this starvation was occuring for the most part
internally . With it's small 256k cache and it's 100MHz ("400") for you marketing junkies), the execution units were starved. Once Northwood (512k L2 cache) arrived, the improvement was huge due to the P4's heavy dependency on it's Trace cache in helping keep the pipline full (as well as other factors).
But now let's take that same "huge engined" car and give it massive fuel lines, carbs, exhaust etc. There will be a point at which the hardest thing to do is get the power from the engine to the ground (more friction). Also our fuel consuption will become amazingly large compared to our fuel economy (not to mention we'll be wanting 100 octane or better). Diminishing returns... So at what point and time will the P4 architecture run out of headroom. And will it lose it's ability to ramp it's bandwidth (internally or externally) first, or will the engine (P4 cpu) just poop out? The current .13micron process is about to run out of headroom, how far will .09 and whatever follows take us? Also,
how much will it cost?
Intel's plan with the P4 architecture is to
continually increase bandwidth everywhere, both within the cpu and externally on the buses,
so that as the GHzs ramp up, the cpu is never starved. Prescott's (the upcoming P4 "3rd edition") larger caches (both L1, and L2) and the fsb being increased to 300MHz (1200) are examples of this. Gigabit LAN and AMD's Hypertransport are also
similar in that respect except they are more useful to the networking equivalent of starvation (lets not even get into concurrency. *evil flashback to my old Professor :evil: from JPL crushing my brain*)
Perhaps a good example of this "bandwidth vs cost$ of technology" is Gigabit ethernet. The controllers for Gbit LAN are far more expensive than 100Mb, but can you actually USE the extra bandwidth provided? Or will the cost of multiple NICs, hdds, and everything else needed to fill that Gbit pipe prove to be prohibitive?
If all this is old hat to you, I apologize for the friggin' classroom session.
