Do you think AMD will eventually enable all 32 PCIe lanes for the CPU die on socket AM4?

[cbn]

Zeppelin has 32 PCIe lanes, but for the current generation of socket AM4 AMD is only enabling 24 PCIe lanes.

But what about for Pinnacle Ridge and X470/B450? Do you think AMD will decide to enable all 32 PCIe lanes?

If not Pinnacle Ridge, then for the 7nm processor?

 

[NTMBK]

More lanes would require more pins out of the CPU, meaning a larger and more complicated socket, and a more complicated and expensive motherboard.

 

[BigDaveX]

It might be possible if they created a "Socket AM4+" and turned some of the unused pins on the current design into PCIe pins. But I doubt they will, considering that ThreadRipper is clearly their intended option for users who need more PCIe connectivity than a stock Ryzen can offer.

 

[moinmoin]

More lanes would require more pins out of the CPU, meaning a larger and more complicated socket, and a more complicated and expensive motherboard.

/topic

Completely answers the question in the title. An AM4 with 32 PCIe lanes would not be AM4 anymore.

 

[Rifter]

Not physically possible without adding pins. so no.

 

[scannall]

Not in AM4. AM5 or whatever follows AM4? Should be on PCIe4/5 by then, so we'll see.

 

[whm1974]

Not in AM4. AM5 or whatever follows AM4? Should be on PCIe4/5 by then, so we'll see.

Hopefully the next gen socket will support a full 32 PCIe lanes. If Intel is still sticking to 16 of them by then, that should give AMD a decent edge.

 

[Topweasel]

As noted. Never. There isn't enough unassigned pins and AMD specifically left out those lanes to include APU support and ZIF socket on this platform. This AM4 is specifically a compromise with OEM's, Mobo companies, and AMD.

 

[cbn]

Hopefully the next gen socket will support a full 32 PCIe lanes. If Intel is still sticking to 16 of them by then, that should give AMD a decent edge.

Yes, Intel is sticking with 16 PCIe lanes (directy connected to the CPU) but the chipset can have up to 24 PCIe 3.0 lanes.

 

[eddman]

Yes, Intel is sticking with 16 PCIe lanes (directy connected to the CPU) but the chipset can have up to 24 PCIe 3.0 lanes.

24? I thought the max was 20 total, 16 for PCIe x16 slots, and 4 for DMI/chipset.

P.S. The 24 number for AM4 is rather misleading. 4 lanes are used for the chipset, so 20 lanes are user available.

EDIT: I misread. Disregard.

 

[cbn]

24? I thought the max was 20 total, 16 for PCIe x16 slots, and 4 for DMI/chipset.

Here is a good link for the Z270:

https://www.pugetsystems.com/labs/articles/Z270-vs-Z170-What-is-the-Difference-877/

Additional PCI-E lanes* 24x PCI-E 3.0

*In addition to the 16 PCI-E 3.0 lanes from the CPU

Z270 at Intel Ark here.

Z270 in comparison to other 200 Series chipsets:

https://www.pugetsystems.com/labs/articles/Z270-H270-Q270-Q250-B250---What-is-the-Difference-876/

 

[eddman]

Here is a good link for the Z270:

https://www.pugetsystems.com/labs/articles/Z270-vs-Z170-What-is-the-Difference-877/

Z720 at Intel Ark here.

Those are chipset connected lanes, not CPU connected lanes. I thought we were talking about CPU lanes.

EDIT: I actually missed the "chipset" part in your first post. My mistake. Need to pay more attention.

 

[cbn]

How about PCIe bifurcation for X470 or X570 (or whatever the following chipset ends up bening called)?

How much is involved with dividing the PCIe x 16 into one PCIe x8 lane and another PCIe x8 made up of two PCIe x4? (This so an adapter card with PCIe bridge chip is not needed to run two PCIe x 4 SSDs in the second PCIe x8 slot)

 

[VirtualLarry]

How about PCIe bifurcation for X470 or X570 (or whatever the following chipset ends up bening called)?

How much is involved with dividing the PCIe x 16 into one PCIe x8 lane and another PCIe x8 made up of two PCIe x4? (This so an adapter card with PCIe bridge chip is not needed to run two PCIe x 4 SSDs in the second PCIe x8 slot)

My understanding is, that for each supported bifurcation of a PCI-E slot, comprising so many lanes, there needs to be a PCI-E "Root Port", with associated Config Space Registers. So that each PCI-E device plugged in can be recognized and supported properly.