do Diffrente processors gain Scaling diffrently (in %) on the same processs shrink?

[YossI]

Im having a bit of an arguement on this.
my friend says:



<<
(assuming the quality of the .18 micron processes are the same((copper etc etc))

And chip A: Tops out at 1.5ghz
While chip B Tops out at 3Ghz.

If you Drop them both to .13(again same process) and chip B Now tops out at 6ghz
Chip A WILL top out at 3Ghz.
>>



is this true? does processors gain the same scalbilty (in %) on the same process shrink?

I dont think so I think it has somthing to do with thier circetry design and distrebution along the processor and its stages...

who's right?

 

[Sohcan]

I'll try filling in for pm while he's on vacation, since he's an EE and I'm more comp architecture....


<< does processors gain the same scalbilty (in %) on the same process shrink? >>

No. There are two main sources of delay in an MPU: gate (transistor) delay and interconnect (wire) delay. While in an ideal process shrink gate delay reduces by the ratio of the Leffs (channel length), wire delay stays the same (ignoring technology improvements, such as copper interconnects). In addition, since MPUs stay roughly the same size over time due increased cache size and microarchitectural additions, absolute wire delay gets worse over time compared to gate delay.

The critical path delays of a given microarchitecture can be more or less interconnect delay driven than another microarchitecture. For an empirical example, just look at the Athlon and P3...they both started at or around 750MHz at .18um. While the P3 hit a wall at 1GHz, the Athlon is at 1.67GHz...though admittedly the current Athlons use copper interconnects, so use the 1.3GHz (aluminum) Duron as a comparison. Its not uncommon for a given microarchitecture to be designed to have a "sweet spot," with the knowledge that its demand will be the highest along one or two particular process shrinks.

 

[YossI]

Thank You!

not only this was a great explantion - but it turns out I was sorta right!

BTW could you explain exeactly what are gate and interconnect delays ?

now I think I now some of this : like Gate delay has to do with how fast the gate switchs... but Im not sure.
and I know nothing on interconnect delays...

Thank you!

 

[Sohcan]

<< could you explain exeactly what are gate and interconnect delays ? >>

Okay, this is where I'm starting to stretch my expertise...as I said, I'm in comp architecture, I'm sure an EE could give a more thorough explanation...

MOS circuits behave like RC (resistance & capacitance) circuits, which is the source of their delay. If I recall correctly the characteristic delay is tau = R*C (the voltage will rise to 1 - 1/e = 63% of its final value at time tau = R*C), such that the voltage will rise and fall exponentially like V(t) = V0(1 - e^(t/RC)).

MOSFET transistors have capacitances between their components (gate, base, source, drain) as well as resistance that contributes to the gate delay. Logically nMOS and pMOS transistors are easy to understand, but I only have a simple understanding of the solid state physics behind their operation, so I can't really give a more detailed explanation....

Interconnect delay is simply due to the fact that electrical signals do not propogate instantaneously (or even at the velocity of light) along wires (those inbetween transistors). Likewise, wires have their own RC behavior: resistance due to the material, and the length and width of the wire. I believe the capacitance is derived from the distance between the wire and the ground plane. I think the reason that wire delay remains constant across process shrinks is because although wire capacitance decreases, resistance increases.

Again, if any EEs want to give a more detailed explanation, be my guest. 🙂

 

[StandardCell]

Sohcan, those are pretty good explanations, I'm very impressed for someone not dealing with silicon directly every day. 😀 I do have a couple of corrections and clarifications though. I'll also throw a few comments of my own as I go.

While it's true that wire delay dominates chip delays/speeds and gates are practically free, it doesn't necessarily mean wire delays stay the same. There are a lot of different issues that change between process nodes, such as temperature operating points shifted higher, thinner wires which are required to meet the routing needs of more densely-packed areas where thinner means higher resistance, and parasitics which change due to different dielectric and other materials and cause signal integrity problems . The wire delays are made up of the intrinsic characteristics of the wire as well as parasitics, i.e. wire to wire delays caused by mutual impedances. Most of them are NOT to ground unless possibly within a cell, since with quite a number of routing layers, the capacitances to ground are basically zero. What's more important than capacitance to ground is inter-wire capacitances (and inductances at 0.13 and lower). These have an impact not only on delay, but on signal integrity - glitching, which causes false switching, and delay, where one line held to one level causes another line near it to not switch as fast because the electric field is holding it at the opposite value to what it wants to switch to.

Yossi, your friend is incorrect. Process shrinks do NOT cause proportional speed increases in that way. It's more like a 30-40% increase AT MOST, and then more if you do architectural cheats like the P4 has through pipelining at the expense of latency and heavy misprediction penalties. You also have the ever present power density and power dissipation problems which are only getting exponentially worse as process shrinks and you drive to include more and more functionality.

 

[Sohcan]

Thanks for the backup. 🙂



<<
While it's true that wire delay dominates chip delays/speeds and gates are practically free, it doesn't necessarily mean wire delays stay the same. >>

You're right, constant was a poor choice of words. Was I under the correct impression that wire delay typically does not reduce by the same factor as gate delay? Though this may be a huge generalization, but how do wire dimensions change across process shrinks when a mask is redrawn? You mentioned wire thickness, but what about length? Is the change in each linear dimension *in general* comparable to the change in dimension of the process size?



<< The wire delays are made up of the intrinsic characteristics of the wire as well as parasitics, i.e. wire to wire delays caused by mutual impedances >>

Since smaller wires should (IIRC) have smaller characteristic capacitance, does the proportion of parasitic to characteristic capacitance increase with shrinking die sizes?

 

[StandardCell]

<< Thanks for the backup. 🙂 >>



Welcome. 😀



<< You're right, constant was a poor choice of words. Was I under the correct impression that wire delay typically does not reduce by the same factor as gate delay? Though this may be a huge generalization, but how do wire dimensions change across process shrinks when a mask is redrawn? You mentioned wire thickness, but what about length? Is the change in each linear dimension *in general* comparable to the change in dimension of the process size? >>



Gates are basically "free" from a delay perspective at smaller and smaller process widths, because they're switching in the single picosecond range in some cases (i.e. simpler A-strength drive inverter). Wire delays just get worse PROPORTIONALLY speaking, however, not from an absolute perspective, plus signal integrity is increasingly a more important issue starting from about the 0.18u process node. It's never a linear change, but the pace of decreasing gate delays has outpaced the decrease in wire delays. I can't really put a percentage on it simply because every design approach is different. And, like I mentioned before, there are other factors such as higher temperature operating points that increase the dissipated power, and things I didn't mention like increasing requirements for routing power (which proportionally increasing leakage currents and higher activity switching ratios are only aggravating) and hardmacro passthroughs in hierarchical designs with large buses.



<< The wire delays are made up of the intrinsic characteristics of the wire as well as parasitics, i.e. wire to wire delays caused by mutual impedances >>

Since smaller wires should (IIRC) have smaller characteristic capacitance, does the proportion of parasitic to characteristic capacitance increase with shrinking die sizes?[/i] >>



It does in part, but then again, the signals are switching ever faster. You need more drivers in line to deal with ramp time problems (i.e. rise/fall times for heavily loaded signals due to wire length or fanout). Capacitances come in two basic varieties - layer-to-layer (vertical) and sidewall (horizontal). If you have long lengths of parallel wires, you have delays and also signal integrity problems where one wire causes the other to be even more delayed due to the wire holding the E-field (aka voltage) the opposite way of wher it wants to switch, or possible glitching on control lines. You also have inductance hampering designs at these small process widths which it didn't before, and that's an ugly problem because it severely impacts the runtimes of the extraction and signal integrity tools. That's a whole other discussion.