Differential Pair Siganalling

[ahock]

Hey can anyone explain how differential pair siganalling work? Basicall these implementation are now common specially on SATA and USB. Instead of lots of busses to carry signals they use only few bus lines but in differential mode. How does the system recognize if dat is 1 or 0

 

[Matthias99]

There's a few different questions you might be trying to ask here. I'm not sure exactly what you want to know.

Most serial communications protocols are pretty simple. You have a data line and a clock. You assert the data you want to send (1 or 0) on the data line, then tick the clock, and the other side reads the data when the clock ticks. Simple. But not very robust.

The biggest problem is line noise. There's always some amount of noise in an electrical connection, especially if it has to run over any appreciable distance (wires tend to act like antennas when they get big enough, plus you can get interference from other nearby wires). With differential signalling, you use two wires, and send your signal twice -- through one wire 'positively' (that is, you send +X volts for '1' and -X volts for '0') and the other 'negatively' (send -X volts for '1' and +X volts for '0'). Since (presumably) you get the same amount N of noise in each wire, what you end up with is:

Positive wire: X + N volts
Negative wire: -X + N volts

Then you can get X (with most or all of the noise removed) by taking the difference of the voltages on the two wires. If your voltage comes out positive, the signal is a '1'; if it's negative, the signal is a '0'. This lets you use much higher communication frequencies, and much longer wires, without degrading your signal too badly. You can get more sophisticated (for instance, using something like QAM, or sending your signals as transitions rather than static voltages), but that's the basic principle.

 

[walla]

The benefits of differential pair signaling are significant.

Differential signaling greatly reduces signal noise. The reason is that if two wires carry a differential signal, and are close enough to be susceptible to the same noise sources, that noise will be cancel in taking the difference. (Ie [X+noise] - [Y+noise] = X-Y).

Differential signaling is faster, too, because of this. Since the noise is much less, the signal-to-noise ratio (SNR) increases. If the signal power is not significantly above the noise power, there is no easy way to distinguish the two. A certain communication technology may require a certain minimum SNR to differentiate a logical "1" from "0"... lowering noise allows you to lower the voltage to maintain that threshold. Therefore, voltage swing can be decreased by lowering noise. This increases the speed at which lines can be switched and data can be transfered.

Differential signalling is becoming more popular in high-speed chip-to-chip communications, too. The HyperTransport technology relies on low-voltage differential signalling (LVDS) to acheive purported bandwidths of up to 22.4 gigabit/sec and is supported by AMD's latest 64-bit chips.

 

[TuxDave]

Originally posted by: walla
Differential signaling is faster, too, because of this. Since the noise is much less, the signal-to-noise ratio (SNR) increases. If the signal power is not significantly above the noise power, there is no easy way to

Adding a little on the SNR part, differential signalling also gives you a larger signal swing. For single ended signalling and a supply voltage of vdd, your signal can only move from 0 to vdd or a range of vdd. If you have differential signalling with:

(first wire)/(second wire)
(0)/(Vdd) Output = 1st-2nd = -Vdd
(Vdd)/0 Output = +Vdd

You take the difference and now you see with a supply voltage of vdd, you can get 2*vdd signal range for free. Well... almost free, the only loss is that now you have to have an extra wire.

 

[blahblah99]

Originally posted by: walla
The benefits of differential pair signaling are significant.

Differential signaling greatly reduces signal noise. The reason is that if two wires carry a differential signal, and are close enough to be susceptible to the same noise sources, that noise will be cancel in taking the difference. (Ie [X+noise] - [Y+noise] = X-Y).

Differential signaling is faster, too, because of this. Since the noise is much less, the signal-to-noise ratio (SNR) increases. If the signal power is not significantly above the noise power, there is no easy way to distinguish the two. A certain communication technology may require a certain minimum SNR to differentiate a logical "1" from "0"... lowering noise allows you to lower the voltage to maintain that threshold. Therefore, voltage swing can be decreased by lowering noise. This increases the speed at which lines can be switched and data can be transfered.

Differential signalling is becoming more popular in high-speed chip-to-chip communications, too. The HyperTransport technology relies on low-voltage differential signalling (LVDS) to acheive purported bandwidths of up to 22.4 gigabit/sec and is supported by AMD's latest 64-bit chips.

 

[blahblah99]

Originally posted by: TuxDave

Originally posted by: walla
Differential signaling is faster, too, because of this. Since the noise is much less, the signal-to-noise ratio (SNR) increases. If the signal power is not significantly above the noise power, there is no easy way to

Adding a little on the SNR part, differential signalling also gives you a larger signal swing. For single ended signalling and a supply voltage of vdd, your signal can only move from 0 to vdd or a range of vdd. If you have differential signalling with:

(first wire)/(second wire)
(0)/(Vdd) Output = 1st-2nd = -Vdd
(Vdd)/0 Output = +Vdd

You take the difference and now you see with a supply voltage of vdd, you can get 2*vdd signal range for free. Well... almost free, the only loss is that now you have to have an extra wire.

To add to what others have said, differential signaling is faster because the required voltage swing is less (ie, half the voltage swing requirement of a single ended signal). This eases slew rate requirements on the drivers (opamps). The noise on the differential pair is cancelled by the common mode rejection ratio of the receiver, assuming that the traces are closer to each other compared to aggressor traces.

If the driver and receiver are synchronous systems, then you dont have to worry about clock recovery. However, if they are asynchronous, then data will have to be encoded using Manchester, NRZ, or any other common encoding techniques to ensure that the receiver can recover the clock.