Die shot of Llano displayed at GF tech. Conference

[busydude]

I guess we need a new APU sub-forum, I took some time to decide where to post this. Anyway, this forum is a bit civilized so.. Discuss.

New information.

The memory controller and northbridge functionality has received a massive makeover due to the increased data needs of an onboard graphics component. Again, the details of the changes will not be made public until much closer to the release of this product. This upgrade in the memory controller will likely not have a large effect on CPU performance, but it was certainly necessary to feed the GPU. It will still be a dual-channel, DDR-3 implementation, but with official support for higher DDR-3 speeds.

It looks to have around 480 stream units, which is one SIMD (80 stream units) larger than the current Redwood GPU that powers the HD 5500 and HD 5600 parts. The chip is going to have multiple clock domains, so the CPU core will run into the 3 GHz range while the GPU portions could see anywhere from 750 MHz to 1 GHz (or potentially slightly higher due to the process it is based upon).

For comparative purposes, the current integrated graphics portions of AMD’s class leading chipsets are based upon a single SIMD design (80 stream units) running between 500 MHz and 750 MHz. These parts are based on TSMC’s 55 nm process, so the new graphics portion of Llano is 1.5 nodes newer. This has allowed AMD to fit a whole bunch more stream units into an area that was typically reserved for the L3 cache on the Phenom II.


The die size overall on the Llano part should be between 170 mm squared and 210 mm squared, based on rough estimates comparing the die size of the 45 nm Phenom IIs with the full L3 cache. It should be an improvement for AMD in terms of manufacturing, but it certainly is not as efficient as their native 45 nm dual core design with 1 MB of L2 cache per core or the Athlon II X4s.

With the recent leaks of Sandy Bridge performance, we know that Llano will not be all that competitive on the CPU side. Certainly it will be an improvement over the current Phenom II parts (just barely), but it will get nowhere near Nehalem or Sandy Bridge performance. AMD is not terribly worried about that right now, as they feel the graphics performance will be more than enough to overtake what Sandy Bridge brings to integrated GPUs.

I am kinda dumb founded by that bolded part.

Source Article

 

[GaiaHunter]

I am kinda dumb founded by that bolded part.

Think 2 things: "PC Console" and future APUs with BD+better GPUs.

 

[Vesku]

Llano is not for the enthusiast crowd, it's meant for laptops and computer as appliance market. Although I'm itching to see what can be done with the GPU and OpenCL.

 

[Idontcare]

Isn't that the same old cropped die-shot that was present in the marketing slides 6 months ago? IIRC there is a die-shot out there that shows the full (or fuller) diemap including all the GPU SP's.

 

[Vesku]

I'd love to see the full die shot if it's out there. This one did seem awfully familiar.

 

[busydude]

Isn't that the same old cropped die-shot that was present in the marketing slides 6 months ago? IIRC there is a die-shot out there that shows the full (or fuller) diemap including all the GPU SP's.

Oh. This is the first time I have seen the die shot. .

 

[bryanW1995]

*snip*
Anyway, this forum is a bit civilized so.. Discuss.

Video has a new sherrif in town, didn't you hear? They're all nice and cuddly now.



I'm excited about llano because my current laptop has hd 3200 integrated. in a year or two every laptop available will offer decent graphics, so that $399 special from hp will actually be able to play games at decent settings.

 

[KingstonU]

I have a hard time believing that this will be 55nm, must be a typo since AMD's CPUs are already at 45nm and their GPUs are already at 40nm. My guess is it's TSMC's 40nm process.

 

[Chiropteran]

I have a hard time believing that this will be 55nm,

It's not.

the current integrated graphics portions of AMD’s class leading chipsets are based upon a single SIMD design (80 stream units) running between 500 MHz and 750 MHz. These parts are based on TSMC’s 55 nm process

"These parts" is talking about the current integrated graphics in various AMD northbridge chips.

 

[ilkhan]

Just to double check, no L3 on llano, right?

 

[busydude]

Just to double check, no L3 on llano, right?

Yup, its basically a shrunk (32nm HKMG) Athlon II with larger L2 and Turbo.

 

[Idontcare]

I'd love to see the full die shot if it's out there. This one did seem awfully familiar.

Oh. This is the first time I have seen the die shot. .

all your answers are belong to here

 

[GaiaHunter]

Yup, its basically a shrunk (32nm HKMG) Athlon II with larger L2 and Turbo.

Or if you prefer to be more positive is basically a shrunk X4 Thuban with no L3.

 

[Martimus]

all your answers are belong to here

For those who don't want to scroll down to the full die shot, I have linked it here:

We have had quite a few discussions based on this full die shot already. One is that it actually appears that there are 12 groups of shaders, not 6 as shown in the cropped shot.

 

[KingstonU]

Originally Posted by KingstonU
I have a hard time believing that this will be 55nm,

It's not.

the current integrated graphics portions of AMD’s class leading chipsets are based upon a single SIMD design (80 stream units) running between 500 MHz and 750 MHz. These parts are based on TSMC’s 55 nm process

"These parts" is talking about the current integrated graphics in various AMD northbridge chips.

Thanks for clearing that up.