Delidded my i7-3770K, loaded temperatures drop by 20°C at 4.7GHz

[BonzaiDuck]

I have no data to back it up but I remember reading that diamond paste is definitely a no-go for bare-die applications because of their etching tendency. I'm sure you're aware of this but I just wanted to bring it back up. It's risky.

It could be risky if you spread it on the die. Or it would be riskier if you spread it on the die. But if you spread it thinly on the CPU side of the IHS and add another silicon-grease to lubricate it, the risk should be considerably less. Especially less, I'd think, if you assure that some or all pressure from HSF spring-loaded assembly is on the IHS, which means attempting to keep the black adhesive intact. I'm trying to figure out how best to make the Pit Crew useful in this endeavor -- point being, later removal of the IHS would require the same razor-blade trick if "adhesion" to stabilize the pressure or provide support along the IHS edge is desired/re-established.

 

[Diogenes2]

I have no data to back it up but I remember reading that diamond paste is definitely a no-go for bare-die applications because of their etching tendency. I'm sure you're aware of this but I just wanted to bring it back up. It's risky.

^ This..

No matter how stable you think the HS/waterblock is there are subtle vibrations that will transfer to the silicon like an microscopic orbital sander .

All of the CPUs I have used 7 Carat with have cleaned the IHS as if I had sanded it..

No matter how small the diamond particles are, some of the layers of the CPU die are only molecules thick. The Diamond particles would be like abrasive boulders.
While I don't know how close the active layers are to the top of the die, I don't think I would risk it.

 

[Idontcare]

Either that or the synthetic micronized diamond. What?! It's 7-carats worth in a tube for about $7. There's enough to do either three IHS caps or both the graphics card plus the CPU heatsinks. You can pay $24 for 24 carats . . .

I think you are thinking of something different than what we were talking about in those last few posts.

We are talking about shimming the IHS between the IHS and the PCB (shimming the collar that touches the PCB) such that it lifts the IHS back off of the CPU by exactly the amount that was initially there in the stock configuration.

Right now we have a bit of an apples to oranges comparison going on. In my test I both replaced the CPU TIM and decreased the thickness of that CPU TIM by virtue of eliminating the gap between the CPU and the underside of the IHS when I removed all that IHS adhesive.

The gap was 0.06mm, now it is zero mm.

So to gain back that 0.06mm gap I need to shim the IHS upwards by 0.20mm off of the PCB (a 0.14mm shim would merely fill the currently existing gap between the PCB and the IHS).

Only once I have reestablished the CPU-to-IHS gap can we compare the resulting temperatures from various CPU TIM replacements to that of the stock CPU TIM because only then will we have established a testing scenario in which we are holding all else constant (the gap being the same is key, of course).

We aren't looking to use the metal shim on the CPU die itself, which is what I gathered you thought we were talking about based on your post regarding the use of IC diamond.

Once the 0.06mm gap is reestablished then I'd have no qualms over using a diamond paste on the CPU silicon die provided the largest particles (not the average of the distribution) is assured to be less than 60 micron.

 

[BonzaiDuck]

^ This..

No matter how stable you think the HS/waterblock is there are subtle vibrations that will transfer to the silicon like an microscopic orbital sander .

All of the CPUs I have used 7 Carat with have cleaned the IHS as if I had sanded it..

No matter how small the diamond particles are, some of the layers of the CPU die are only molecules thick. The Diamond particles would be like abrasive boulders.
While I don't know how close the active layers are to the top of the die, I don't think I would risk it.

Well, that leaves you with the lesser options . . . . which are lesser. Anyone know how thick the silicon substrate or whatever it's called above the CPU circuitry?

 

[Idontcare]

^ This..

No matter how stable you think the HS/waterblock is there are subtle vibrations that will transfer to the silicon like an microscopic orbital sander .

All of the CPUs I have used 7 Carat with have cleaned the IHS as if I had sanded it..

No matter how small the diamond particles are, some of the layers of the CPU die are only molecules thick. The Diamond particles would be like abrasive boulders.
While I don't know how close the active layers are to the top of the die, I don't think I would risk it.

The exposed silicon die that you see with your eyes is actually the backside of the CPU, itself hermetically sealed with a silicon nitride layer so the bare silicon is not exposed.

The layers of concern that you are thinking about are safely hidden away by being mated (soldered) to the PCB layer.

That said, you do not want to press a small hard ball into a brittle material. In Materials Science we do this as a standard test for determining a material's fracture toughness and hardness.

The diamond paste will act as nanoindentors, the overhead IHS will act as the downforce, and the silicon die will become the "specimen under test". Silicon does not have a good fracture toughness.

Toughness is the ability of a material to resist crack propagation.

source

If the nanoindentors (the diamond particulates) are smaller than the gap between the IHS and the CPU then the downforce transmitted from the IHS through a diamond particulate and into the silicon will be negliable, no concern then.

The pyramidal diamond indenter of a Vickers hardness tester.

But I would not do it on a bare exposed die without the aid of mechanically robust standoffs. I've done those tests in college and at TI with Knoops hardness test and Vickers hardness test machines, and the outcome is always the same - test ends with mechanical failure of the specimen under test

 

[Idontcare]

Well, that leaves you with the lesser options . . . . which are lesser. Anyone know how thick the silicon substrate or whatever it's called above the CPU circuitry?

~500 micron.

The analogy is this - imagine the silicon substrate is a 10 story tall building. The active circuitry would be a 6" layer sitting at the very top of that 10-story building.

Then they flip it upside down and solder it onto the PCB.

The stuff we are doing on the backside of the silicon substrate has virtually no ability to effect the active circuits beyond that of creating cracks (inducing mechanical failure) or creating a thermal/electrical gradient that becomes problematic to first or second-order.

 

[OVerLoRDI]

Interesting information regarding the spacing. For anyone going through this process would you recommend restoring that .06mm space between the dye and the IHS? Or would this only really apply for using diamond TIM?

 

[HondaCop]

Interesting information regarding the spacing. For anyone going through this process would you recommend restoring that .06mm space between the dye and the IHS? Or would this only really apply for using diamond TIM?

Good question. I would like to know as well since I'm running right now with the adhesive, so my IHS is resting on the die.

 

[BonzaiDuck]

The exposed silicon die that you see with your eyes is actually the backside of the CPU, itself hermetically sealed with a silicon nitride layer so the bare silicon is not exposed.

The layers of concern that you are thinking about are safely hidden away by being mated (soldered) to the PCB layer.

That said, you do not want to press a small hard ball into a brittle material. In Materials Science we do this as a standard test for determining a material's fracture toughness and hardness.

The diamond paste will act as nanoindentors, the overhead IHS will act as the downforce, and the silicon die will become the "specimen under test". Silicon does not have a good fracture toughness.



If the nanoindentors (the diamond particulates) are smaller than the gap between the IHS and the CPU then the downforce transmitted from the IHS through a diamond particulate and into the silicon will be negliable, no concern then.



But I would not do it on a bare exposed die without the aid of mechanically robust standoffs. I've done those tests in college and at TI with Knoops hardness test and Vickers hardness test machines, and the outcome is always the same - test ends with mechanical failure of the specimen under test

Well, we know we can significantly reduce the load temperature of the die with better TIM. We're pretty darn sure that all the suggested remedies would work for some period of time.

So we're trying to reduce any risk that the entire enchilada will stop working before one might anticipate.

Simple is best, although any precision work complicates things. Forgetting about the adhesive layer for the moment and using a dremel, you could cut a rectangular slot in the IHS top surface so that it just fits over the processor; then lap the top a bit; then lap the bottom flange of the IHS until the surfaces are level or nearly level with the slightest potential gap between the die and the HSF-base.

Then use your AS5 or NT-H1-whatever, increase direct heat transfer and lower temperatures.

Pain-in-the-A**, and what do you have left? Something, I guess . . .

 

[Yuriman]

What I'd like is a 0.14mm shim (or perhaps 0.13 or 0.12mm) to minimize risk of crushing the edges of the die when I mount my waterblock.

 

[Kenmitch]

I think at this point lapping the.bottom of the IHS isnt a good think. I wonder if the tolerances would hold true on all chips tho. Its possible.some.fluctuation would be possible. Might explain the rubbery bonding agent.

 

[BonzaiDuck]

I think at this point lapping the.bottom of the IHS isnt a good think. I wonder if the tolerances would hold true on all chips tho. Its possible.some.fluctuation would be possible. Might explain the rubbery bonding agent.

Yeah -- I thought about "rubbery" and may have mentioned it. And I just thought of the implications of lapping the bottom flange of the IHS. What you'd like is a way to remount the IHS so that the die can mate with the cooler-base, but so that the IHS provides support for the HSF and avoids much stress or pressure on the die -- or otherwise allows just enough pressure to accommodate a thin layer of TIM . . .

 

[Idontcare]

Simple is best, although any precision work complicates things. Forgetting about the adhesive layer for the moment and using a dremel, you could cut a rectangular slot in the IHS top surface so that it just fits over the processor; then lap the top a bit; then lap the bottom flange of the IHS until the surfaces are level or nearly level with the slightest potential gap between the die and the HSF-base.

The IHS is ~3mm thick, the CPU die sticks up a mere 0.5mm above the PCB. You has a lot of grinding in your future if you intend on shaving that 3mm IHS down to being just 0.5mm tall

Might as well go IHS-less and just build up a 0.55mm tall metal collar shim.

I think at this point lapping the.bottom of the IHS isnt a good think. I wonder if the tolerances would hold true on all chips tho. Its possible.some.fluctuation would be possible. Might explain the rubbery bonding agent.

I'm sure the tolerances are spec'ed so that the outcome was basically the same (the IHS never rests on the CPU), but the actual gap itself is probably maintained by the CPU TIM so that the resulting thermal properties are essentially identical from chip to chip.

If they didn't carefully control the resulting thickness of the CPU TIM then you'd probably see a silly-wide distribution of stock operating temperatures with the "golden samples" being the ones who happened to have a thinner CPU TIM by accident.

 

[BonzaiDuck]

The IHS is ~3mm thick, the CPU die sticks up a mere 0.5mm above the PCB. You has a lot of grinding in your future if you intend on shaving that 3mm IHS down to being just 0.5mm tall

Might as well go IHS-less and just build up a 0.55mm tall metal collar shim.



I'm sure the tolerances are spec'ed so that the outcome was basically the same (the IHS never rests on the CPU), but the actual gap itself is probably maintained by the CPU TIM so that the resulting thermal properties are essentially identical from chip to chip.

If they didn't carefully control the resulting thickness of the CPU TIM then you'd probably see a silly-wide distribution of stock operating temperatures with the "golden samples" being the ones who happened to have a thinner CPU TIM by accident.

What about foam art-board for a shim? It will compress from 1/4" thickness. If necessary, you could use two cut from the same stencil. It's non-conductive, and you'd think it wouldn't be affected by the heat except to make it less flexible . . . Probably would need only one shim, when you think of the paper backing and compressed plastic foam. Or -- if you were to get rid of the IHS altogether. Wht then happens to the clip-assembly. You just count on the HSF holding the CPU in place?

 

[HondaCop]

http://www.overclock.net/t/1258439/ivy-bridge-3770k-heat-spreader-thermal-grease-testing

Seems like someone has already tried the Liquid Metal Ultra on the bare die and it survived to tell a tale. Sorry if you all have seen this already.

 

[ICD7]

Originally Posted by Idontcare View Post
The exposed silicon die that you see with your eyes is actually the backside of the CPU, itself hermetically sealed with a silicon nitride layer so the bare silicon is not exposed.

The layers of concern that you are thinking about are safely hidden away by being mated (soldered) to the PCB layer.

That said, you do not want to press a small hard ball into a brittle material. In Materials Science we do this as a standard test for determining a material's fracture toughness and hardness.

The diamond paste will act as nanoindentors, the overhead IHS will act as the downforce, and the silicon die will become the "specimen under test". Silicon does not have a good fracture toughness.



If the nanoindentors (the diamond particulates) are smaller than the gap between the IHS and the CPU then the downforce transmitted from the IHS through a diamond particulate and into the silicon will be negliable, no concern then.



But I would not do it on a bare exposed die without the aid of mechanically robust standoffs. I've done those tests in college and at TI with Knoops hardness test and Vickers hardness test machines, and the outcome is always the same - test ends with mechanical failure of the specimen under test

No problem with a bare die, IC Diamond is used extensively on bare die applications Notebooks, GPU's with no damage, I even have a gpu application with a contact pressure test of over 90 psi and no damage.

While diamond is harder than most materials it is only incrementally so The metal oxides used in thermal compounds like Aluminium oxide (what they use in sandpaper) will etch glass like diamond are a 9 on the MOHS scale vs 10 for diamond.

IC Diamond is mix of several different sizes, engineered for full contact between particles (as with most pastes)and so to provide full contact on the mating surfaces.

Load is evenly distributed over your billions of contact points, essentially no difference and perhaps better distribution than a solid shim with a more complete contact.

Where people have a problem with the "etch" is due to improper cleaning related to improper use of solvents where they scrub for removal rather then let the solvent do the work.

I have a video that when I find the time to finish editing it I will post on about 600 forum threads to correct the disinformation. This video shows a 95 PSI application to a copper oxide surface that is delicate enough to be polished to a bright shine as demonstrated with a bare finger in only a few seconds, the coating is only 200 atoms thick ( about 1-2% of the later etched lettering you see on an IHS) yet with proper application and removal no damage can be found.

 

[cbn]

The exposed silicon die that you see with your eyes is actually the backside of the CPU, itself hermetically sealed with a silicon nitride layer so the bare silicon is not exposed.

The layers of concern that you are thinking about are safely hidden away by being mated (soldered) to the PCB layer.

That said, you do not want to press a small hard ball into a brittle material. In Materials Science we do this as a standard test for determining a material's fracture toughness and hardness.

The diamond paste will act as nanoindentors, the overhead IHS will act as the downforce, and the silicon die will become the "specimen under test". Silicon does not have a good fracture toughness.



If the nanoindentors (the diamond particulates) are smaller than the gap between the IHS and the CPU then the downforce transmitted from the IHS through a diamond particulate and into the silicon will be negliable, no concern then.

~500 micron.

The analogy is this - imagine the silicon substrate is a 10 story tall building. The active circuitry would be a 6" layer sitting at the very top of that 10-story building.

Then they flip it upside down and solder it onto the PCB.

The stuff we are doing on the backside of the silicon substrate has virtually no ability to effect the active circuits beyond that of creating cracks (inducing mechanical failure) or creating a thermal/electrical gradient that becomes problematic to first or second-order.

Great info!!

 

[ICD7]

^ This..

No matter how stable you think the HS/waterblock is there are subtle vibrations that will transfer to the silicon like an microscopic orbital sander .

All of the CPUs I have used 7 Carat with have cleaned the IHS as if I had sanded it..

No matter how small the diamond particles are, some of the layers of the CPU die are only molecules thick. The Diamond particles would be like abrasive boulders.
While I don't know how close the active layers are to the top of the die, I don't think I would risk it.

I am not convinced on this one

If that were true, Aluminum oxide the preferred abrasive for etching glass and is used in AS5,Shin Etsu, Mx-4 etc. would be causing wholesale slaughter of IHS serial numbers with an MOHS of 9 and similar particle sizes.

Nothing is going to move if your sink is tightened down properly, your describing physics that doesn't exist unless your sink is flapping in the breeze.

 

[moonbogg]

Copper shim stock available to be delivered to your doorstep. Thickness starting at .001" up to whatever you need in increments of .001". Copper would fill the gap, be soft and pliable and transfer heat like a mofo. Lap everything and put a super thin film of TIM on both sides of copper sheet and I bet temps drop like a rock.

http://www.mcmaster.com/#shim-stock/=iqge21

 

[blckgrffn]

This thread is on Anandtech main page via the twitter feed because it is awesome

(just when you think twitter is absolutely useless!)

 

[moonbogg]

This thread is on Anandtech main page via the twitter feed because it is awesome

(just when you think twitter is absolutely useless!)

Whats even more awesome is that this thread shows that Intel straight up LIED about heat density being the issue, but we already knew that right? I suggest buying some of that copper shim stock from two posts above....OR link again right here:

http://www.mcmaster.com/#shim-stock/=iqge21

 

[HondaCop]

Well guys, I couldn't resist and took the plunge. I used Liquid Metal Ultra as this: CPU DIE>>LMU>>IHS>>LMU>>H100

The system booted up and it's running normally.

Here is my system:

ASUS P8Z77-V
Intel i7-3770K (de-lidded)
EVGA GTX670 FTW
8GB (2x4GB) Samsung Low Profile 30nm 1600 DDR3
Corsair H100
Corsair TX-750 power supply

As far as performance when compared to MX-4, so far I have to say there isn't much of a drop in temps on idle load. I set my system to all stock/default settings, which means that everything is on AUTO within the BIOS.

For idle temps, this is what I have so far (LinX|21000|20 runs, is running as I type this):

Idle @ 1.6Ghz (turbo is enabled) using MX-4

Core 1 - 27.6C
Core 2 - 19.3C
Core 3 - 25.2C
Core 4 - 26.4C
CPU package - 27.8C

Full Load @ 3.7Ghz (turbo enabled) using MX-4

Core 1 - 50.5C | +22.9C increase from idle
Core 2 - 47.5C | +28.2C increase from idle
Core 3 - 54.3C | +29.1C increase from idle
Core 4 - 48.7C | +22.3C increase from idle
CPU package - 54.6C | +26.8C increase from idle


Now here are the results with Liquid Metal Ultra...


Idle @ 1.6Ghz (turbo is enabled) using Liquid Metal Ultra

Core 1 - 27.9C
Core 2 - 18.3C
Core 3 - 24.7C
Core 4 - 26.8C
CPU package - 28.1C

As you can see, idle temps are almost identical to the ones with MX-4. Now let's see how it did on full load.

Full Load @ 3.7Ghz (turbo enabled) using Liquid Metal Ultra

Core 1 - 42.6C | +14.7C increase from idle | -7.9C drop from MX-4
Core 2 - 38.9C | +20.6C increase from idle | -8.6C drop from MX-4
Core 3 - 44.4C | +19.7C increase from idle | -9.9C drop from MX-4
Core 4 - 42.4C | +15.6C increase from idle | -6.3C drop from MX-4
CPU package - 44.7C | +16.6C increase from idle | -9.9C drop from MX-4

As you can see, idle temps remained almost identical BUT temps on full load showed a considerable drop. With MX-4, the increase delta from idle to load was in the 20s, while with Liquid Metal Ultra, the increase from idle to load was in the teens!

As stated before, full load was based on 3.7GHz while running LinX with a problem size of 21000 for 20 runs. With LMU on full load, none of the cores touched 50C during the entire stress run! They maxed out in the mid to upper 40s. :thumbsup:

EDIT: And another thing I noticed is that the temps were more tighter among the four cores. Before, I was getting wild temp fluctuations between all four cores, I even started a new thread earlier today asking if that was normal. With LMU, the temps were almost identical between all 4 cores, separated on average by +-5C from one another.

 

[Idontcare]

Whats even more awesome is that this thread shows that Intel straight up LIED about heat density being the issue, but we already knew that right? I suggest buying some of that copper shim stock from two posts above....OR link again right here:

http://www.mcmaster.com/#shim-stock/=iqge21

Heat density is still very much "a" problem IMO, and I base that assertion on the following data:

Notice that at the same clockspeeds, running on the same cooler, mobo, ram, OS, etc, both CPU's are essentially running at the exact same temperature under the same LinX load but the IB CPU is running 43W lower in power usage.

This delta is even more significant if you consider that the power numbers there are total power at the wall. The power usage of just the 2600k CPU is 203W versus 160W for the IB CPU...that's a 21% reduction in CPU power consumption but the core temps hit the same operating temperature of ~86°C.

160W for a 160mm^2 die is 1W/mm^2 for Ivy Bridge.

203W for a 216mm^2 die is 0.93W/mm^2 for Sandy Bridge.

(die size reduced to 0.74x but power is reduced by only 0.79x)

Power density increased with the move to 22nm, as expected, which is why I see the same temps for IB that I see for SB despite having replaced the CPU TIM on the IB.

It is true though that power-density doesn't explain why the CPU temps were so much more higher on the stock CPU, prior to the CPU TIM replacement, as that is clearly not due to power density...it would appear to be due to the large gap that exists between the IHS and the CPU.

As for the shim, I already ordered a roll of 0.203mm metal shim from the supplier linked in that earlier post by yottabit. Will probably be a week before I get it though

 

[Idontcare]

Well guys, I couldn't resist and took the plunge. I used Liquid Metal Ultra as this: CPU DIE>>LMU>>IHS>>LMU>>H100

The system booted up and it's running normally.

Here is my system:

ASUS P8Z77-V
Intel i7-3770K (de-lidded)
EVGA GTX670 FTW
8GB (2x4GB) Samsung Low Profile 30nm 1600 DDR3
Corsair H100
Corsair TX-750 power supply

As far as performance when compared to MX-4, so far I have to say there isn't much of a drop in temps on idle load. I set my system to all stock/default settings, which means that everything is on AUTO within the BIOS.

For idle temps, this is what I have so far (LinX|21000|20 runs, is running as I type this):

Idle @ 1.6Ghz (turbo is enabled) using MX-4

Core 1 - 27.6C
Core 2 - 19.3C
Core 3 - 25.2C
Core 4 - 26.4C
CPU package - 27.8C

Full Load @ 3.7Ghz (turbo enabled) using MX-4

Core 1 - 50.5C | +22.9C increase
Core 2 - 47.5C | +28.2C increase
Core 3 - 54.3C | +29.1C increase
Core 4 - 48.7C | +22.3C increase
CPU package - 54.6C | +26.8C increase


Now here are the results with Liquid Metal Ultra...


Idle @ 1.6Ghz (turbo is enabled) using Liquid Metal Ultra

Core 1 - 27.9C
Core 2 - 18.3C
Core 3 - 24.7C
Core 4 - 26.8C
CPU package - 28.1C

As you can see, idle temps are almost identical to the ones with MX-4. Now let's see how it did on full load.

Full Load @ 3.7Ghz (turbo enabled) using Liquid Metal Ultra

Core 1 - 42.6C | +14.7C increase
Core 2 - 38.9C | +20.6C increase
Core 3 - 44.4C | +19.7C increase
Core 4 - 42.4C | +15.6C increase
CPU package - C | +16.6C increase

As you can see, idle temps remained almost identical BUT temps on full load showed a considerable drop. With MX-4, the increase delta from idle to load was in the 20s, while with Liquid Metal Ultra, the increase from idle to load was in the teens!

As stated before, full load was based on 3.7GHz while running LinX with a problem size of 21000 for 20 runs. With LMU on full load, none of the cores touched 50C during the entire stress run! They maxed out in the mid to upper 40s. :thumbsup:

EDIT: And another thing I noticed is that the temps were more tighter among the four cores. Before, I was getting wild temp fluctuations between all four cores, I even started a new thread earlier today asking if that was normal. With LMU, the temps were almost identical between all 4 cores, separated on average by +-5C from one another.

That's awesome :thumbsup:

 

[BonzaiDuck]

That's awesome :thumbsup:

. . . As long as our speculated misgivings do not materialize . . .

With the Indigo Xtreme, the surfaces actually have to heat up to cause the pad to "set." Ultra may be a thicker formulation that just Liquid Pro -- I wouldn't be sure. But it goes on with a brush applicator.

An 8C improvement is nothing to sneeze at. So you wonder what the voltage requirement might be for 4.7 Ghz.

ICD7!! Long time . . . no see!!

I think his handle observes "where he's comin' from." Like I said -- "The Threads have eyes."

That's reassuring, ICD7.