Curious about heterogeneous cores & AMD APUs

[onething]

(Please correct me if I'm wrong)

I recall reading an article / rumor about a group; they were able to use the GPU portion on the APU to process more intensive CPU tasks, while the CPU took on the less intensive, but more complicated tasks. You lose your GPU, but you get a much more powerful CPU.
Isn't this the direction heterogeneous cores are trying to go?

Anyway, I don't know where to find the article anymore or if anything came of it. Perhaps someone here can shed some light or rumors on any developments?

 

[NostaSeronx]

http://www4.ncsu.edu/~yyang14/hpca2012.pdf
http://news.ncsu.edu/releases/wmszhougpucpu/
^--???

Or, something else?

As in you mean Kaveri(Steamroller) and Kabini/Temash(Jaguar unless it is only a Leopard feature) that comes with new words to learn?
A LCU supports both its native CPU instruction set and the HSA intermediate language (HSAIL) instruction set.
A TCU supports only the HSAIL instruction set.

^
A latency compute unit (LCU) is a generalization of a CPU.
A throughput compute unit (TCU) is a generalization of a GPU.

^-- (Look up: Heterogeneous System Architecture: A Technical Review)

Also, it states HSAIL instruction set... well Graphic Core Next fully uses it.
http://www.amd.com/jp/Documents/GCN_Architecture_whitepaper.pdf
Ctrl+F: Instruction Set
Shortcut:

Spoiler

The new GCN ISA was designed to facilitate industry standards. AMD’s Heterogeneous System Architecture (HSA) is envisioned as a model for heterogeneous
computing. It defines how CPUs and GPUs communicate and includes a virtual ISA (the HSA Intermediate Language), which is hardware agnostic. HSAIL code
is dynamically compiled for the underlying hardware, and thus compatible with CPUs and GPUs from any vendor. GCN fully supports HSAIL, in part because
of the shift to a more flexible instruction set.

http://amddevcentral.com/Resources/hc/OpenCLZone/Events/Documents/GCN_Webinar_public.pdf
Look at the instructions.