CPCHardware：2nd gen AMD EPYC will have 64 cores, 256 Mo (!) L3, 8x DDR4-3200 and 128 PCIE-4 lines

[csbin]

https://twitter.com/CPCHardware/status/925348852147908608

 

[Yotsugi]

https://twitter.com/CPCHardware/status/925348852147908608

OH BOY
THEY ARE GOING IN FOR THE KILL

 

[Topweasel]

The more I look at it the more possible it is. I don't see AMD doubling up on L3 (16MB per CCX, 4 CCX per die) because a 32MB 16c Ryzen seems kind of out there. But I really doubt this late in the game they would be able to change the dies that much from their 48c roadmap. I mean Zen 2 dies should be hitting production late 2018 to early 19. They should already have been doing tape outs and you can't just add another CCX and call it good. The module makes this easier but not that quickly.

 

[Yotsugi]

The more I look at it the more possible it is. I don't see AMD doubling up on L3 (16MB per CCX, 4 CCX per die) because a 32MB 16c Ryzen seems kind of out there. But I really doubt this late in the game they would be able to change the dies that much from their 48c roadmap. I mean Zen 2 dies should be hitting production late 2018 to early 19. They should already have been doing tape outs and you can't just add another CCX and call it good. The module makes this easier but not that quickly.

The last roadmap that mentioned Zen+ (or Zen2) is ancient.

 

[Topweasel]

The last roadmap that mentioned Zen+ (or Zen2) is ancient.

Starship was a relatively new addon from late 2016. Not that ancient and honestly lines up with an early to mid 2019 release. They have a year+ to get it to market. That's not enough time to change the plans this late in the game unless they stated 48 to give some room for redundancy and see what Yields would look like. I know AMD has to really push the core advantage they have while they can. I am just not too sure about this change.

 

[Yotsugi]

I am just not too sure about this change.

Is there anything wrong with pushing moar corez for datacenter?
Besides, Intel can't do it because muh monolithic dies.

 

[Topweasel]

Is there anything wrong with pushing moar corez for datacenter?
Besides, Intel can't do it because muh monolithic dies.

I didn't say there was. I just doubt that AMD in 6 months has gone from one design to another for a CPU that is only just over a year away no matter how important it is for AMD to push for more cores.

 

[CatMerc]

The more I look at it the more possible it is. I don't see AMD doubling up on L3 (16MB per CCX, 4 CCX per die) because a 32MB 16c Ryzen seems kind of out there. But I really doubt this late in the game they would be able to change the dies that much from their 48c roadmap. I mean Zen 2 dies should be hitting production late 2018 to early 19. They should already have been doing tape outs and you can't just add another CCX and call it good. The module makes this easier but not that quickly.

Amusingly, it does. Changing a die built from modular parts is taken down from months to hours, by AMD's own words.

And adding more of a repeating structure like L3 cache into your die is not a problem engineering wise, it's a cost problem.

I do wonder how they plan to reuse 64MB of L3 cache dies in consumer. Cut it to 32MB for yields? Maybe give the top X models full 64 to have differentiation?

 

[Topweasel]

Amusingly, it does. Changing a die built from modular parts is taken down from months to hours, by AMD's own words.

Oh I am sure it does. But there is all sorts of other work that needs to be done including prototyping, tape outs, qualifications, so year they no longer are mapping out millions of transistors for the CPU cores but that is part of the game. So it makes a 4-5 year development process 2.5 to 3 years. That's still 3 years. This is basically suggesting what should have been virtually a finalized chip, and saying AMD stopped the presses, had them add whole nother module without affecting the rest of the timeline. I have a problem with that. I would welcome being wrong though.

 

[Yotsugi]

I do wonder how they plan to reuse 64MB of L3 cache dies in consumer. Cut it to 32MB for yields? Maybe give the top X models full 64 to have differentiation?

Assuming it truly is 16cores per 2 DDR channels, they need a LOT of L3 to keep them fed.

 

[wahdangun]

Hmm 128 lane pcie-4 ?? What an Overkill.

So is this supposed to be starship ? And Zen 2 ?? So it will be 7 NM?

 

[NTMBK]

It's called "Starship" because you need an antimatter reactor to provide enough power. Jesus.

 

[Topweasel]

Hmm 128 lane pcie-4 ?? What an Overkill.

So is this supposed to be starship ? And Zen 2 ?? So it will be 7 NM?

Yeah EPYC would receive very limited benefit from the Zen+ refresh. So the next Epycs we will see will be Zen 2 and therefore 7nm. It's part of the reason for core count increase.

 

[wahdangun]

Yeah EPYC would receive very limited benefit from the Zen+ refresh. So the next Epycs we will see will be Zen 2 and therefore 7nm. It's part of the reason for core count increase.

It's really surprising that CPC can get that information, especially I'm expecting at least next year before we got some leak, so is that mean CPC have EPYC 2 in their hand, like they do in ryzen months before it was launch

 

[Yotsugi]

It's called "Starship" because you need an antimatter reactor to provide enough power. Jesus.

But it's not an Intel chip.

 

[NTMBK]

But it's not an Intel chip.

For which we should be grateful- that would need a Zero Point Module, and we all know how hard it is to get your hands on one of those.

 

[raghu78]

These specs look monstrous and if AMD bring this to market in H1 2019 it will be a clean kill. AMD need to make sure GF can supply enough wafers to meet demand. AMD said t hey will be taping out 7nm parts before end of 2017. I think Navi at TSMC 7nm and Zen 2 at GF 7nm. After seeing the GF 7nm IEDM paper I think AMD will use 7SoC for EPYC Rome. 7SoC uses 6T libraries and brings about 65% area reduction vs 14LPP 7.5T libraries .7SoC is good for designs running at 3.5 Ghz and server chips don't need to run at 4+ Ghz as they are optimized for throughput.

It's really surprising that CPC can get that information, especially I'm expecting at least next year before we got some leak, so is that mean CPC have EPYC 2 in their hand, like they do in ryzen months before it was launch

Since AMD is taping out now for EPYC Rome to be ready for H1 2019 its possible that CPC has got info from reliable sources. No guarantees here though. They could also be bluffing.

 

[Yotsugi]

These specs look monstrous and if AMD bring this to market in H1 2019 it will be a clean kill. AMD need to make sure GF can supply enough wafers to meet demand. AMD said t hey will be taping out 7nm parts before end of 2017. I think Navi at TSMC 7nm and Zen 2 at GF 7nm. After seeing the GF 7nm IEDM paper I think AMD will use 7SoC for EPYC Rome. 7SoC uses 6T libraries and brings about 65% area reduction vs 14LPP 7.5T libraries .7SoC is good for designs running at 3.5 Ghz and server chips don't need to run at 4+ Ghz as they are optimized for throughput.

7SoC is good for everything considering where its fmax lands.
7HPC is squarely an IBM node with 17 layers of metallization.

 

[raghu78]

7SoC is good for everything considering where its fmax lands.

yeah i think AMD will use 7SoC for servers and notebooks. Next gen consoles will definitely use 7SoC.

7HPC is squarely an IBM node with 17 layers of metallization.

Desktop Zen 2 (Ryzen 7/5/3/TR) will need 7HPC to hit 5 Ghz.

 

[Yotsugi]

Desktop Zen 2 (Ryzen 7/5/3/TR) will need 7HPC to hit 5 Ghz.

No, check the curves.

7HPC is aimed at >5.5GHz operation.

 

[Phynaz]

I need to open a Twitter account. I could tweet all kinds of BS just like Canard does.

 

[Yotsugi]

I could tweet all kinds of BS just like Canard does.

CPC is pretty accurate though.
Besides they are the ones to get both K8 and Zen ES.

 

[raghu78]

No, check the curves.

7HPC is aimed at >5.5GHz operation.

No. GF stated 7SoC is optimized for designs running at 3.5 Ghz. The comparison on the curve with 14nm at 1x normalized freq and >1.4x for 7SoC at same power would put the normalized freq at 2.5 Ghz for 1x and 5.0 Ghz for 2.0x. 7SoC curve stops at 1.7x. 4.25 Ghz. 7HPC goes upto 2.1x (5.25 Ghz)

 

[Phynaz]

CPC is pretty accurate though.
Besides they are the ones to get both K8 and Zen ES.

Throw enough crap at the wall some is bound to stick.

 

[Yotsugi]

GF stated 7SoC is optimized for designs running at 3.5 Ghz.

For ARM trash using HD libs? Ye.

But generally fmax goes up exactly 40% for 7SoC over 14LPP.