Could MIPS be a threat to ARM and x86?

[dma0991]

MIPS Architecture Crashes ARM, X86 Party: 28nm chips to operate at 1.5GHz, Run Android 4.0

How different would MIPS be compared to ARM in terms of overall performance and power consumption? I still do think that people would buy tablets or smartphones more based on the brand, visual appearance and user friendliness of the OS with the processor being a blackbox, unknown to the user.

 

[jsedlak]

Having coded in both IA32/Y86 and MIPS Assembly (briefly), I like the former a lot more.

Not that it has any say in whether or not MIPS is a good platform.

 

[cbn]

Here is the article from the link....

P.S. Global Foundries 28nm.....So they will be building these with "Gate first" xtors?

MIPS Architecture Crashes ARM, X86 Party: 28nm chips to operate at 1.5GHz, Run Android 4.0 ICS
Reported by Theo Valich on Friday, December 9 2011 9:53 am

The debate between "PC Everywhere" and "Post PC" is currently raging in the boardrooms and between consumers and there are mostly two bases everybody discusses: X86 or ARM architecture. Well, not anymore…

MIPS Architecture Crashes ARM, X86 Party: 28nm chips to operate at 1.5GHz, Run Android 4.0 ICS

After spending most of their time outside the limelight, MIPS Technologies marked a very strong week by announcing that the company successfully started the manufacturing of the brand new high-performance, three-way microprocessor chip using 28nm-SLP (Super Low Power) process node at GlobalFoundries Fab 1 in Dresden, Germany.

The chip was a development between MIPS Technologies and eSilicon Corporation, with the expected clock between 1GHz as worst-case scenario, while the optimal clock target is 1.5GHz. Given that the chip is in manufacturing right now, it will take about three months to deliver first chips to customers. Still, bear in mind the 1GHz minimum, 1.5GHz optimal figure.

The week continued with MIPS Technologies making another joint announcement, this time with Chinese manufacturer Aionovo (no relationship to Lenovo). Aionovo debuted NOVO7, world's first android 4.0 "Ice Cream Sandwich" tablet for the non-subsidized price of $100, i.e. you can expect that carriers will be offering them for free with subscription.

This tablet is powered by Ingenic Semiconductor JZ4770 SoC, containing a single MIPS32-based processor core operating at 1GHz, paired with Vivante GC860 GPU featuring complete Full HD acceleration (video processing engine).

While this 7" tablet won't be sold out of China until at least spring-to-summer period, the magnitude of this announcement speaks volumes. Our industry sources working at companies that manufacture x86 and ARM-based solutions almost unanimously expressed their concern. If Ice Cream Sandwich ends up working smooth on a tablet for $100, all it takes is a decent CPU upgrade, capacitive touch-screen instead of the ultra-cheap resistive one and voila, a competitor for the current and future ARM and X86 based designs is born.

MIPS is not a small player either. While ARM likes to boast that the company ships billions of devices per year, MIPS also powers numerous set-top-boxes, TVs, network switches, automotive and avionics systems - competing against ARM. MIPS Technologies had management issues through their long history but things started to change last year, after Sandeep Vij was named CEO. The company went through reorganization and the result is a more nimble competitor.

One of people giving thumbs up to MIPS is Andy Rubin, Senior VP of Mobile, Google Inc. He stated that he is "thrilled to see the entrance of MIPS-Based Android 4.0 tablets into the market". Furthermore, Andy stated that Google wants to see more high-performance MIPS solutions, as "low cost, high performance tablets are a big win for mobile consumers and a strong illustration of how Android's openness drives innovation and competition for the benefit of consumers around the world."

MIPS already speaks 64-bit

Unlike ARM, MIPS developed a 64-bit architecture quite some time ago, with the products based on MIPS64 shipping inside networking equipment. According to information available, Cavium Networks, NetLogic Microsystems and even CISCO are either shipping or evaluating MIPS64 architecture for their network products. In comparison, ARM is now talking about 64-bit but the company did not announce 64-bit part as of today. 32-bit Cortex-A15 and derived products will debut in products next year, and 64-bit is only expected in 2013-2014 timeframe.

While MIPS originally worked with their own licensors using less advanced processing nodes, the launch of 28nm part which targets as high clock as the fastest clocked Cortex-A9 speaks volumes. While SOC needs to be bundled with a powerful graphics, image processing and connectivity systems, ARM just might find themselves in dead heat with MIPS Technologies. Also, bear in mind that Qualcomm already heavily modifies Cortex architecture and flat out refuses to specifically name ARM in their marketing materials, NVIDIA is developing its own 64-bit ARM-based architecture… the number of companies using future reference Cortex cores in high end parts might drop to just a few players.

Good Enough Computing coming back to haunt ARM?

By launching the already mentioned Aionovo NOVO7 tablet, the 32-bit JZ4770 is already operating at 1GHz, while the upcoming 28nm parts are expected to scale to 1.5GHz and beyond. Should the company optimize their 32-bit and 64-bit MIPS architecture alongside 28nm-SLP and introduce 20nm-LP and -SLP nodes at GlobalFoundries and TSMC, MIPS Technologies just might have a ticket to ride to pressure ARM and their gigantic ecosystem. Naturally, Intel is also coming to the mix with 22nm based Silvermont, who is set to debut in 2013.

Power consumption also seems to be the strong side of the MIPS architecture. The JZ4770 SOC consumes only 0.25W under 100% CPU and video engine load (1080p playback), which is significantly less than ARM competitors. Naturally, as you beef up the GPU and add a second core, the power consumption will go up, but still below ARM-based products. And when ARM posed a question of "good enough" computing to counter Intel and AMD claims of high-performance requirements for desktop computing, did the company thought that a competitor might say the same question to them? Is MIPS making lower power consuming parts than ARM for "good enough computing"?

While we won't know the answer for this for quite some time, but the battle is on. MIPS vs. ARM vs. AMD vs. Intel.

 

[nenforcer]

Having coded in both IA32/Y86 and MIPS Assembly (briefly), I like the former a lot more.

I think you mean the latter? MIPS has a much more modern and orthogonal architecture (32 32-bit registers, etc) compared to the 40 year old monstrosity which is X86.

Needless to say its questionable whether one ultra low power 64-bit MIPS core is better than a dual or even quad core 32-bit ARM processor. Most tablets and cell phones still don't use more than 1-2GB of RAM so the need for a 64-bit chip isn't necessary.

 

[ncalipari]

I think that in the future code will be independent from the specific CPU platform, very much like Java promised, allowing users to consume information via platform-agnostic browsers.

 

[ElFenix]

i wondered where MIPS would be in all this. it was a parallel project to the original RISC project and has powered everything from high end graphics workstations (jurassic park was done on MIPS machines) to game consoles (N64). mostly seems used for set top boxes and dvd/br players at the moment. i presume ARM has more experience designing for anemic power at this point, though.

 

[cbn]

This is the highest performance MIPS processor I could find on the company website:

http://www.mips.com/products/cores/32-64-bit-cores/mips32-1074k/#specifications


Base Core: 1074Kf (with FPU)
Configuration: dual core
Process: 40nm G (TSMC)
Libraries: TSMC 12 track, MVt/OD
Frequency: >1.2 Ghz, 1.5 GHz
Coremark/MHz (per core) 2.55
DMIPS/MHz (per core) 2.03
Power: 0.36 mW/Mhz, 0.43 mW/MHz
Area: 4.1 mm2

Now compare this to ARM Cortex A9: http://www.arm.com/products/processors/cortex-a/cortex-a9.php (click performance tab for specifications)

Cortex A9 Dual Core Hard Macro Implementation
Process: 40nm G (TSMC)
Frequency: 2000 Mhz (performance optimized),800Mhz (power optimized),
Performance (total DMIPS) : 10,000, 4000
Energy efficiency (DMIPS/Mw): 5.26, 8.0
Total power at target frequency: 1.9W, .5W

So it appears the MIPS 1074f core achieves ~80% the drystone MIPS/MHz compared to the Cortex A9 core.

Trying to equalize the two CPU designs (with respect to Drystone MIPS and power consumption) I come up with the following:

1.2 Ghz MIPS 1074f (with FPU) dual core = 4872 DMIPS. 432mW power consumption.
800 Mhz Cortex A9 (power optimized) dual core = 4000 DMIPS, 500mW power consumption.

So overall, the 1.2 Ghz MIPS dual core (using TSMC 40nm G) actually beats the 800 Mhz Cortex A9 dual core (using TSMC 40nm G) according to the marketing specs taken from both companies.

 

[jhu]

The future is wide open. 20 years ago, ARM was bit player, MIPS was going to take over the high-end, and x86 was relegated to consumer-level computers. Now ARM is all over the low-end, x86 is consumer-level and HPC (no one saw that one coming), and MIPS is in routers.

 

[cbn]

The future is wide open. 20 years ago, ARM was bit player, MIPS was going to take over the high-end, and x86 was relegated to consumer-level computers. Now ARM is all over the low-end, x86 is consumer-level and HPC (no one saw that one coming), and MIPS is in routers.

Well according to my example in post#7 they did a pretty good job of scaling down.

Now I would like to see how they would fare scaling back up on future process nodes where heat density becomes more of an issue.

How much single threaded performance can they give us before the closely packed xtors become too hot?

 

[jsedlak]

I think you mean the latter? MIPS has a much more modern and orthogonal architecture (32 32-bit registers, etc) compared to the 40 year old monstrosity which is X86.

Needless to say its questionable whether one ultra low power 64-bit MIPS core is better than a dual or even quad core 32-bit ARM processor. Most tablets and cell phones still don't use more than 1-2GB of RAM so the need for a 64-bit chip isn't necessary.

I spoke correctly, but I (a) know very little about assembly, (b) used it only in school type of situations and (c) realize that my personal opinion in this area has very little founding on any factual or otherwise impartial data.

 

[Arkadrel]

ARM is getting into Windows... MIPs isnt (currently).

I dont think MIPs is gonna threaten ARM, not in the near forseeable future.
ARM might pull a fast one, and become a hit with mainstream pcs (pulling sales away from intel and amd).

I think if ARM started by working its way up, first putting their strongest ARM CPUs they can make into Laptops, that would be a good way to start things off. Then work their way up again to desktops at some point if they can manage to get close to Intel/AMD level of performances.

 

[Tuna-Fish]

As far as the instruction sets are concerned, the proposed 64-bit arm is *very* close to 64-bit mips. The ISA really doesn't impose any power or performance differences to the platforms.

However, ARM engineers have *a lot* more experience in low-power integrated things than these guys do, and as Intel has shown, it's not about the ISA, it's about the implementation for it.

 

[soccerballtux]

hm. could happen.

 

[ncalipari]

However, ARM engineers have *a lot* more experience in low-power integrated things than these guys do, and as Intel has shown, it's not about the ISA, it's about the implementation for it.

Well I would disagree with this. Intel is a profitable company because they hold a patent on their ISA, which is the instruction set that the market wants at this point, locking out competition.

 

[Tuna-Fish]

Well I would disagree with this. Intel is a profitable company because they hold a patent on their ISA, which is the instruction set that the market wants at this point, locking out competition.

That was in no way my point. My point was that Intel has shown that if you are good enough doing the implementation, it doesn't matter that your isa is horrible and clunky, it'll still be fast.

 

[denev2004]

Can some one tell me the strength of MIPS over ARM?
I think they share a same idea from RISC..
I know they have a different way of business operation. Besides that is there anything else concerns about tecnical details?

 

[Arachnotronic]

I find it hysterical that people think that an instruction set is what determines performance. It's the micro-architecture that matters (the actual design of the chip) these days. Decode is such an incredibly small part of any modern chip's transistor budget that it really, really doesn't matter.

If you're *really* smart (like Intel), you do things like adding a decoded micro-ops cache which allows the decode stage to be power gated in SNB.

AMD's Bulldozer's ISA is x86-64, with even some goodies Intel doesn't have (FMA4, XOP), yet SNB is better. Why? The actual microarchitecture, the actual circuit designs, the quality of the caches, etc.

Good luck to ARM trying to compete with Intel's years and years of experience being the best at high performance CPU uArchs & designs. And MIPS? lol...Intel's ultrabook fund is larger than MIPS' entire market cap.

 

[ncalipari]

Decode is such an incredibly small part of any modern chip's transistor budget that it really, really doesn't matter.

Decoding is the most power-expensive step on a modern x86 CPU.

 

[aphelion02]

Decoding is the most power-expensive step on a modern x86 CPU.

Which is separate from its (small) transistor budget, which was what his point was. And which also doesn't mean it is the determinant of the performance of the CPU itself.

 

[Cerb]

Can some one tell me the strength of MIPS over ARM?

Older MIPS designs couldn't compete with newer CPUs, especially as x86 started gaining features that RISC zealots thought CISC couldn't get, and edged into workstation RISC int performance. In the midst of that, SGI, who bought MIPS, decided to go all Itanium, and spun MIPS off again.

In just a few years, MIPS transformed from having biggest baddest CPUs to having CPUs that went inside of cheap hardware, just to run firmware. MIPS today is like SH. It's alive, and well, but just skating along.

The strengths of ARM are mostly implementation IP (patents and such), and plenty of engineers with experience in low power implementations of processors. The A9 and Longsoon both throw away any prior strengths and weaknesses related to slow (in ARM's case) and in-order operation.

ARM's ISA is generally fairly MIPS-like. Running a 400MHz in-order CPU, it could be argued that ARM's ISA gives it major strengths, but going OOOE, and with memory far away, it's all a bunch of nothing. Bring on the R&D budgets.

I think they share a same idea from RISC..
I know they have a different way of business operation. Besides that is there anything else concerns about tecnical details?

Not enough to be concerned with, I don't think. ARM will have a bit smaller binaries, on average, but I doubt it will matter too much. ARM has a real advantage in making efficient CPUs, but the non-CPU parts are coming to so dominate performance and power that MIPS has a fair chance, and while MIPS' ISA is fractured like ARM's, a typically-compatible subset is well-supported by most FOSS software. ARM's aggressive business practices, and regular (if small by Intel standards) cash flow and profit, give them their real edge over MIPS, as it may concern any wide consumer markets.

 

[Blitzvogel]

I wonder if all the PS1 and PS2 programmers out there still remember how to program on MIPS?

 

[nenforcer]

I wonder if all the PS1 and PS2 programmers out there still remember how to program on MIPS?

Them and the legion of Nintendo 64 programmers as well.

It's good to see MIPS trying to be aggressive in this space, which they should have been aggressively pursuing years ago.

Hopefully they haven't lost too much market share to ARM already so they can still compete and not get squeezed out of the marketplace entirely.

 

[pitz]

These days, with code being so portable and written in high-level languages, whoever can deliver the cheapest, and most power-efficient processors wins.

Funny isn't it, how we had the big RISC versus CISC (ie: x86) wars in the 1990s, and RISC was supposed to win, but we're still all running Intel CPU's, and the instruction set is more bloated than its ever been?

 

[Absolution75]

These days, with code being so portable and written in high-level languages, whoever can deliver the cheapest, and most power-efficient processors wins.

Funny isn't it, how we had the big RISC versus CISC (ie: x86) wars in the 1990s, and RISC was supposed to win, but we're still all running Intel CPU's, and the instruction set is more bloated than its ever been?

Actually new Intel Processors are RISC when you get to the heart of it, x86 is still "CISC" but it gets decoded into RISC. If intel allowed us to program in whatever micro-op language they use, you could bypass the decode stage. Though this is incredibly impracticable because it generally changes with every new architecture. All those CISC x86 instructions do get reduced to multiple RISC instructions though - so RISC did win.


Goes to what Intel17 was saying:

I find it hysterical that people think that an instruction set is what determines performance. It's the micro-architecture that matters (the actual design of the chip) these days. Decode is such an incredibly small part of any modern chip's transistor budget that it really, really doesn't matter.

If you're *really* smart (like Intel), you do things like adding a decoded micro-ops cache which allows the decode stage to be power gated in SNB.

AMD's Bulldozer's ISA is x86-64, with even some goodies Intel doesn't have (FMA4, XOP), yet SNB is better. Why? The actual microarchitecture, the actual circuit designs, the quality of the caches, etc.

 

[jhu]

Actually new Intel Processors are RISC when you get to the heart of it, x86 is still "CISC" but it gets decoded into RISC. If intel allowed us to program in whatever micro-op language they use, you could bypass the decode stage. Though this is incredibly impracticable because it generally changes with every new architecture. All those CISC x86 instructions do get reduced to multiple RISC instructions though - so RISC did win.

Actually, RISC did not win. There was no winner. Even traditionally "RISC" architectures (such as some implementations of POWER) decode instructions into micro-ops (with some decoding to several micro-ops).