Computer Architecture question (clock buffer?)

[wilki24]

I'm taking a Computer Architecture class, and the instructor briefly went over clock buffers this evening, but I didn't quite grasp what their purpose was. I figured I'd come home, and look it up on the internet, but I can't seem to find a basic definition for what a clock buffer is, and what it's basic purpose is. Can someone help me with that?

Thanks!

 

[Matthias99]

Jeez... I went *through* a low-level systems class, and a circuit design class, and I don't remember ever talking about a "clock buffer". We talked about clock circuits, timing delays, setup and hold times, clock skew, overclocking, CMOS transistor physics... but no, no clock buffers. You sure you got the right term?

 

[wilki24]

Yep, I'm sure. It has to do with propogation delay, but I'm not sure exactly what it does or when you'd use it. I *think* that is delays a signal by a certain amount of time, but when I asked the instructor if you'd use one in a certain place on a circuit, he got excited and said that was very bad design technique. He's not a native English speaker, so sometimes I think the language barrier gets in the way. This was at the end of class tonight, and we ran out of time, otherwise I would have asked for more information.

Here is a link to some clock buffers sold by fujitsu:

http://edevice.fujitsu.com/fj/MANUAL/MANUALx/CELLSPECH/SM01-84202/CE81_UNIT/U.CLOCK_BUFFER_FAMILY.html

 

[CTho9305]

Hopefully pm doesn't mind me quoting him:

The usual way to distribute a clock is with a pseudo H-tree. Here's how we did it on McKinley. (Link: http://www.intel.com/design/itanium2/download/isscc_2002_6s.pdf)http://www.intel.com/design/itanium2/download/isscc_2002_6s.pdf
See slide 6.
ODCS => on die clock shrink. It's a technique for inducing rapid clock frequency changes to induce critical speed path failures for rapid debugging.
PLL => phased locked loop. Generates a faster clock phase matched with a lower frequency clock.
SLCB => Second level clock buffer. Circuit that buffers the clock and allows minor adjustments.

So you use it to reduce clock skew across the chip.

 

[sgtroyer]

In general, a buffer passes a signal unchanged, but with higher drive strength. (Drive strength relates to how much load a signal can drive). Since the clock goes to thousands of registers on a large chip, it must have a huge drive strength. The clock source (typically an on chip PLL), doesn't have a large drive strength, so the clock must be buffered several times.

I can go into further detail if you'd like, not sure quite what answer you're looking for.

 

[calbear2000]

Simply put, a buffer = 2 inverters

 

[Matthias99]

Ah, I get it. We talked about that, but the term "clock buffer" never came up (or I missed that lecture). These sorts of things are used to both regenerate and slow down a clock signal, allowing you to keep chips that are physically separate in step.

Apparently there's an entire *journal* on clock skew in circuit design. Who knew?

 

[Mday]

Originally posted by: Matthias99
Ah, I get it. We talked about that, but the term "clock buffer" never came up (or I missed that lecture). These sorts of things are used to both regenerate and slow down a clock signal, allowing you to keep chips that are physically separate in step.

Apparently there's an entire *journal* on clock skew in circuit design. Who knew?

i did =P

 

[Burner]

buffers are used for two things in chips:
1. To create delay (usually used to fix hold time)
2. To increase drive strength of a signal.
As mentioned earlier because the clock is distributed to 1000s of flops in the design the clock path is usually a tree to distribute a good clock signal to all of the different flops.
When you do this you use clock buffers rather then regular buffers. Clock buffers are generally slightly bigger then regular buffers, but they have some advantages over the traditional buffer.
The main thing a clock buffer does is provide an equal rise time and fall time for the signal. If they are different and you do a bunch of them in a row then the difference can magnify. This difference can cause clock skew between different parts of the chip so that one flop gets a posedge at a different time then the flop that it is talking to. This can make it difficult to meet setup and hold requirements.
For example flop A is driving a signal through a bunch of logic to flop B and the clock is unbalanced.
Clock for flop A:
_____|--|_____|
clock for flop B:
_|---------|__|
Looking at this you can see if data starts to transmit on the posedge of flop A, goes it has to travel very quickly to get to flop B or it will miss the posedge. But if they were balanced it would have much more time.

 

[wilki24]

Thank's everyone for the answers! It's one of the few times that google has failed me!

Now I just need to figure out how to design a 4 byte register file for tonight's homework ;-)

 

[CTho9305]

Originally posted by: wilki24
Thank's everyone for the answers! It's one of the few times that google has failed me!

Now I just need to figure out how to design a 4 byte register file for tonight's homework ;-)

A bunch of flipflops, 2 muxes, and 1 or 2 decoders (you'll need 1 for the write enable signal, and if you want, you can also put the data through a decoder. The alternative would be to put the data on ALL the register inputs).

 

[wilki24]

I'm finding that the course subject material isn't nearly as hard to decipher as the instructor's directions are :-(

Got the register file done though. This is actually a very interesting class. Yesterday, we learned the difference between SRAM and DRAM. Being an Anandtech reader for 4-5 years now, and being in the hardware business for a little longer than that, it's pretty cool to actually learn how some of the underlying technology works.