Clock cycle disparity and quad pumping

[Zerxez]

My memory is Ballistix DDR2 1000 I have mildly over-clocked it to approx DDR2 @ 1066, each module is clocked at an actual 533mhz (1066/2=533mhz) My stock FSB on my E6600 is 1066 (quad pumped) for an actual clock of 266Mhz (1066/4=266).

What this means to me is that the data transfer rate is 1066Mhz equivilant. However the actual clock of the memory is literally 533Mhz and the FSB/northbridge chip is literally clocked at 266Mhz.
Can someone explain how data transfers across this bus? I am in dual channel mode (2x1GB memory sticks) so technically this memory is interleaved and while I understand dual channels I don't understand how it moves across the bus.

Does quad pumped mean that it can take two full RAM cycles of data from each DIMM for a single clock cycle of the north bridge chip? Does it load that data into one or two separate registers?

 

[BrownTown]

quad pumped means it transmits on clock high, clock low, rising edge and falling edge.

 

[Zerxez]

Ok, so that is a total of 4 data transfers per clock. 266*4=1064 The memory is at 533Mhz only rising edge and falling edge, but not High and low. My question is does the data move from rising edge / falling edge on one RAM clock to rising edge and clock high on the NB and then rising edge and falling edge on the second clock of RAM to falling edge and clock low on the NB??

 

[BitByBit]

Intel's 'Quad-pumped' FSB utilises two signals 90' out-of-phase with eachother, both of which transmit data on the rising and falling edges of the clock cycle.
Your 1066MHz DDR2 actually runs at an internal frequency of 266MHz, which incidently, is the reason for DDR2's increased latency over DDR; one internal clock cycle is now equivalent to double the number of external clocks, and it is the number of external clock cycles CAS latency is measured in.
Regarding the apparent disparity between the FSB and memory speed on Intel systems, the Northbridge acts as a kind of buffer between the two. Between the memory and NB we have two memory channels, both of which transmit data on the rising and falling edges of the clock cycle. Between the NB and CPU, we have the FSB as discussed.
The main difference between the two is that each DDR2 module transmits two lots of data per external cycle (533MHz, of four per internal cycle), where the FSB transmits four. Since your system is probably running in dual channel mode however, your memory is able to provide your CPU with twice the bandwidth it can handle, and the only advantage your memory provides at your current FSB over DDR2-533 is latency.

 

[Peter]

Front side bus: It is a QDR bus, transferring four bits per clock per line, and it's 64 bits wide. What Intel calls "FSB1066" is 266 MHz QDR.

RAM: DIMMs are 64 bits wide. DDR2 RAM externally transfers one bit per clock cycle; your DDR2-1066 RAM uses DDR transmissions at 533 MHz. Now internally, DDR2 RAM halves its input clock before going into the core. The core is four-issue, and produces four bits of data in one such internal clock cycle: Four bits are read in the time of two external clock cycles, and then are serialized into an external transmission of four bits in two more cycles. operating frequency, you'll have kind of a bandwidth match. Latencies on the RAM are /much/ higher than on the CPU bus though.

 

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