Clear something up about ECC + Registered DIMMs

[CrutchIsHeavy]

I know what each are individually and I know they can exist at the same time on a DDR DIMM.

Registered memory has a register that delays all info transfered to the module by one clock cycle.

ECC corrects single-bit errors and dectects double-bit errors therefore causing delays while it checks these errors.

The questions are:

Can ECC do its job in the same time Register does its job?

Or does the info have to been transfered to the register and then checked for error correction (or vice versa), therefore adding up the two delays?

-Crutch

 

[SUOrangeman]

pm can prolly answer this. Just thinking out load, I doubt that a 2 cycle hitwould even be noticed. There's at least 100 million cycles per second as it is. And it's not like those 2 extra cycles will continue to propagate (i.e., 2-cycle hit, then 4-cycle hit, then 6, etc.)

-SUO