Confusing sentence:
"DDR3 latencies are numerically higher because the I/O bus clock cycles by which they are measured are shorter; the actual time interval is similar to DDR2 latencies (around 10 ns)."
It's not that a bus cycle is shorter with DDR3 but it the RAM is faster?
So DDR2 1066 PC2-8500+ at CL5 is faster than DDR3 1066 PC2-8500+ at CL7?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.