Cisco OWNZ

[TuxDave]

Originally posted by: Shockwave

Originally posted by: Goosemaster
Their 3750 supports 32Gbits/s:Q

New to this? Marconi...
"Marconi provides a complete line of multiservice switch routers that support ATM/IP/MPLS protocols and scale from 2.5 Gbps to 480 Gbps."

480 > 32

😛

Psh.... I'm currently designing a hardware datapath that can handle roughly an effective 12Tbps. Of I'm cheating as the effective bit rate comes after decompression and using parallel channels. 🙂

 

[Shockwave]

The testing has been a headache. Ack.

12Tbps datapath eh? What kind of link? I assume its a LAN link, say from servers to databases? Thats freaking massive.....

 

[TuxDave]

But then again, remember I'm cheating with compression. :-D

Semiconductor Research Corporation

It has been shown that approximately 10 Tb/s of information needs to be transferred to the writers of a maskless lithography system by the 50 nm generation to be able to write a 300 mm wafer layer per minute, which is in line with current mask-based systems. This calls for a highly parallel datapath architecture. Assuming that the writers will be implemented on the same chip, data compression would be implemented to allow for lower input rates. Issues that need to be analyzed are power consumption, compression ratio, and chip area required to attain a certain throughput.

We have recently designed a scaled down version of a datapath for a maskless lithography chip. The chip incorporates LZ-77 data compression, as well as an SRAM writer interface circuitry. It implements eight parallel decompression paths, Huffman, LZ, runlength, memory, as well as framing and error detection.

 

[Shockwave]

Originally posted by: TuxDave
But then again, remember I'm cheating with compression. :-D

Semiconductor Research Corporation

It has been shown that approximately 10 Tb/s of information needs to be transferred to the writers of a maskless lithography system by the 50 nm generation to be able to write a 300 mm wafer layer per minute, which is in line with current mask-based systems. This calls for a highly parallel datapath architecture. Assuming that the writers will be implemented on the same chip, data compression would be implemented to allow for lower input rates. Issues that need to be analyzed are power consumption, compression ratio, and chip area required to attain a certain throughput.

We have recently designed a scaled down version of a datapath for a maskless lithography chip. The chip incorporates LZ-77 data compression, as well as an SRAM writer interface circuitry. It implements eight parallel decompression paths, Huffman, LZ, runlength, memory, as well as framing and error detection.

So your focusing on machine specific datapaths then, not LAN / WAN links......

 

[Goosemaster]

Originally posted by: Astaroth33
Cisco is a vendor, but not the only vendor. Try not to be a fanboi before you know all the facts.

So you're a "future CCNA, future CCNP, future CCIE, future EE, future CE", eh? How much do you know now?

JackSquat.....

Basically math and science ...

I have a LONG way to go. Regardless of what path I take, these certifications, and the Nortel ones which I checked out, are something I would like to one day have. I am studying to become an EE, but I am still a long way off. In the mean time, I do calculus and work on my network at home😀

 

[Goosemaster]

Originally posted by: Shockwave

Originally posted by: TuxDave
But then again, remember I'm cheating with compression. :-D

Semiconductor Research Corporation

It has been shown that approximately 10 Tb/s of information needs to be transferred to the writers of a maskless lithography system by the 50 nm generation to be able to write a 300 mm wafer layer per minute, which is in line with current mask-based systems. This calls for a highly parallel datapath architecture. Assuming that the writers will be implemented on the same chip, data compression would be implemented to allow for lower input rates. Issues that need to be analyzed are power consumption, compression ratio, and chip area required to attain a certain throughput.

We have recently designed a scaled down version of a datapath for a maskless lithography chip. The chip incorporates LZ-77 data compression, as well as an SRAM writer interface circuitry. It implements eight parallel decompression paths, Huffman, LZ, runlength, memory, as well as framing and error detection.

So your focusing on machine specific datapaths then, not LAN / WAN links......

Unless there is some parallel(not serial) medium I have yet to hear about😀

Seriously, you little lithography toy sounds fun😀

What boggle my mind either the array or flash devicesthat provide 12Tbps to start with:Q

 

[Shockwave]

Originally posted by: Goosemaster

Originally posted by: Shockwave

Originally posted by: TuxDave
But then again, remember I'm cheating with compression. :-D

Semiconductor Research Corporation

It has been shown that approximately 10 Tb/s of information needs to be transferred to the writers of a maskless lithography system by the 50 nm generation to be able to write a 300 mm wafer layer per minute, which is in line with current mask-based systems. This calls for a highly parallel datapath architecture. Assuming that the writers will be implemented on the same chip, data compression would be implemented to allow for lower input rates. Issues that need to be analyzed are power consumption, compression ratio, and chip area required to attain a certain throughput.

We have recently designed a scaled down version of a datapath for a maskless lithography chip. The chip incorporates LZ-77 data compression, as well as an SRAM writer interface circuitry. It implements eight parallel decompression paths, Huffman, LZ, runlength, memory, as well as framing and error detection.

So your focusing on machine specific datapaths then, not LAN / WAN links......

Unless there is some parallel(not serial) medium I have yet to hear about😀

Seriously, you little lithography toy sounds fun😀

What boggle my mind either the array or flash devicesthat provide 12Tbps to start with:Q

You'd be suprised what I've heard of people trying to do with load sharing..... 😕