chips sizes, 65, 45,32,25nm,etc
- Thread starter bwanaaa
- Start date
Cogman
Lifer
- Sep 19, 2000
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I couldn't find any definitive answers. I always believed it to be transistor size, but I guess thats not true. http://en.wikipedia.org/wiki/65_nanometer
Something on the order of the effective gate length. In other words it is related (but not always exactly) the distance between the source and the drain.
Just sort of an example:
http://www.nec.co.jp/techrep/e...Images/060511p44-1.jpg
So that *could* be called a 50nm transistor, but maybe thats like their 65nm process
Just sort of an example:
http://www.nec.co.jp/techrep/e...Images/060511p44-1.jpg
So that *could* be called a 50nm transistor, but maybe thats like their 65nm process
The short answer is that yes, smaller numbers represent shrinking transistors. (And closer together)
Wikipedia seems to be saying that it's a reference spec, based on some kind of memory cell rather than every CPU. I take that to mean that it's about the manufacturing process, rather than the exact measurement of the result. The 45nm process doesn't produce exactly 45nm transistors, but they will definitely be smaller than those created in a 65nm facility.
Wikipedia seems to be saying that it's a reference spec, based on some kind of memory cell rather than every CPU. I take that to mean that it's about the manufacturing process, rather than the exact measurement of the result. The 45nm process doesn't produce exactly 45nm transistors, but they will definitely be smaller than those created in a 65nm facility.
SRAM cell sizes are another way of showing scaling, but they don't always scale the same as gate length does. However since a large proportion of a modern CPU is in fact SRAM it is actually probably a better metric than gate length in terms of predicting size scaling. For example the following chart shows different CMOS processes in production and you can see that even processes at the same node can have different gate lengths and SRAM cell sizes.
http://www.realworldtech.com/i...ticles/iedm-2007-2.gif
http://www.realworldtech.com/i...ticles/iedm-2007-2.gif
I have heard that it is the thinnest line that can be produced by the process. But there are many other limitations in the actual process that increase this process somewhat so the thickness of the lines (looking from the top-down) is usually a bit bigger than the process name and can vary depending on the functino of the line and its local environment.
ITRS defines process nodes based on the average size of part of a particular type of circuit. Specifically, a process is a "45nm" process if the transistors in a 6T SRAM cell are within a certain size range.
So, first, what's a 6T SRAM cell? SRAM is the type of memory used for caches on processors. One "cell" stores one bit of data, and it's called a "bit cell". The dominant circuit used for these cells nowadays has either 6 or 8 transistors (I'm not sure which is more common). Back when people walked to school, through 6 feet of snow, up hill both ways, the cells often contained just 4 transistors, but that style has become a very poor choice for a few reasons. The size of a bit cell is significant because there are millions of copies of the cell on modern processors, so any savings in the bit cell area translates to a good savings in the area of the whole chip. As it turns out, the way they're arranged on a chip is also very friendly to manufacturing, so they can use the very smallest sizes that can be made reliably. You could make a very over-simplified characterization of a process based on this property (this single number on its own really isn't useful for much more than marketing).
If you look at this Intel 45nm SRAM cell, the horizontal shapes form transistor gates. The vertical dimension is referred to as the "gate length", and the distance from the top edge of one to the top edge of the next is referred to as the "poly pitch" (pitch = distance, poly = polysilicon = the material normally used for transistor gates). I think the ITRS definition of 45nm requires that this number is around 150nm (I can't find the exact number). If you look at the SRAM picture, note that the gate length isn't equal to the distance between two gates. The poly pitch is quite a bit larger than 2 gate lengths.
I labeled the Intel SRAM cell here, but that's probably not very helpful for most people (we're seeing one layer too few for it to be clear).
Now, there are a few dimensions that people actually think of when they hear "45nm". The most common would be one of three things:
1) When drawing layout in a CAD program, the vertical dimension of the transistor gate shapes.
2) When that shape is actually printed, what the vertical dimension is.
3) The actual length of the path that the gate is controlling. Take a look at this horrible drawing I made - the length of the path is just the part between the source and drain (labeled "Y"), and as you can see, it's less than the length of the gate (note that "length" is left-right in this picture; "width" would be perpendicular to the screen). By having the diffusions (the source and drain) extend underneath the gate, transistors can be made to perform better. I think this is the dimension usually referred to as "effective" length.
Corrections appreciated if I got anything wrong
.
So, first, what's a 6T SRAM cell? SRAM is the type of memory used for caches on processors. One "cell" stores one bit of data, and it's called a "bit cell". The dominant circuit used for these cells nowadays has either 6 or 8 transistors (I'm not sure which is more common). Back when people walked to school, through 6 feet of snow, up hill both ways, the cells often contained just 4 transistors, but that style has become a very poor choice for a few reasons. The size of a bit cell is significant because there are millions of copies of the cell on modern processors, so any savings in the bit cell area translates to a good savings in the area of the whole chip. As it turns out, the way they're arranged on a chip is also very friendly to manufacturing, so they can use the very smallest sizes that can be made reliably. You could make a very over-simplified characterization of a process based on this property (this single number on its own really isn't useful for much more than marketing).
If you look at this Intel 45nm SRAM cell, the horizontal shapes form transistor gates. The vertical dimension is referred to as the "gate length", and the distance from the top edge of one to the top edge of the next is referred to as the "poly pitch" (pitch = distance, poly = polysilicon = the material normally used for transistor gates). I think the ITRS definition of 45nm requires that this number is around 150nm (I can't find the exact number). If you look at the SRAM picture, note that the gate length isn't equal to the distance between two gates. The poly pitch is quite a bit larger than 2 gate lengths.
I labeled the Intel SRAM cell here, but that's probably not very helpful for most people (we're seeing one layer too few for it to be clear).
Now, there are a few dimensions that people actually think of when they hear "45nm". The most common would be one of three things:
1) When drawing layout in a CAD program, the vertical dimension of the transistor gate shapes.
2) When that shape is actually printed, what the vertical dimension is.
3) The actual length of the path that the gate is controlling. Take a look at this horrible drawing I made - the length of the path is just the part between the source and drain (labeled "Y"), and as you can see, it's less than the length of the gate (note that "length" is left-right in this picture; "width" would be perpendicular to the screen). By having the diffusions (the source and drain) extend underneath the gate, transistors can be made to perform better. I think this is the dimension usually referred to as "effective" length.
Corrections appreciated if I got anything wrong
.
silverpig
Lifer
- Jul 29, 2001
- 27,703
- 12
- 81
I usually refer to it as the size of the feature you can put down using your lithographic process. Where I work we can do ~1 micron with optical lithography, and ~70 nm with ebeam. The systems aren't very sophisticated and if we need better we can go to another lab for it.
TuxDave is right....
Its called the drawn gate length to be perfect... not the effective gate length... its the length between the drain and source (or gate, not sure)...
As the length of transistor shrinks, more can be accomodated inside one chip as before, hence processor power increases....
However I wonder what would happen after "sandy bridge" - 16nm
They might still be able to shrink it, but i doubt it can shrink below 1 nm, its the basic atom size....
How ever ppl say there are methods like fusion lithography and x ray lithography, which can let us achieve even narrower circuits.....
TuxDave, are u into microprocessors and chips and transistors professionally? I mean, like do u have some degree or somethng...?
Its called the drawn gate length to be perfect... not the effective gate length... its the length between the drain and source (or gate, not sure)...
As the length of transistor shrinks, more can be accomodated inside one chip as before, hence processor power increases....
However I wonder what would happen after "sandy bridge" - 16nm
They might still be able to shrink it, but i doubt it can shrink below 1 nm, its the basic atom size....
How ever ppl say there are methods like fusion lithography and x ray lithography, which can let us achieve even narrower circuits.....
TuxDave, are u into microprocessors and chips and transistors professionally? I mean, like do u have some degree or somethng...?
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