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Do you have the process details for Intel 14nm node?
There is nothing at the 14nm node that measures 14nm. It is a liars contest.
If you think that Intel is the best liar of the semiconductor industry, you should back up your claims with the actual numbers. And, follow the advise of Scott Thompson, a former Intel Fellow:
http://www.eetimes.com/document.asp?doc_id=1262887&page_number=1
Everyone "lies" about their geometries.
Regardless of your desperate desires to pin Intel's 14nm node as a fraud, they're far and away ahead of all of their competitors. Get over it.
Also, if you're going to request that someone back up their claims, perhaps you should do the same:
Sorry, but the argument that it's not a 14nm process because nothing measures 14nm is ludicrous. Everyone in the industry knows that the designation hasn't represented an actual number for quite some time, rather it's representative of the gains in performance and density that would be expected from each transition with a bit of rounding. Basically, if you want to call Intel's 14nm process a 20nm process instead (just making up that number by the way) then you'd have to call TSMC's '16nm' and the common platform's '14nm' somewhere around 25nm. (And who knows when they'll actually show up to the game.)
As for details, a few tidbits regarding the 14nm process have been publicly disclosed in this presentation - http://files.shareholder.com/downlo...d94ca36f56c/Jefferies_May_2013_Holt_Final.pdf - but that's about it. The area scaling chart (page 13) implies that Intel's 14nm should see an SRAM cell size somewhere under 0.05 um^2.
Hans de Vries
Senior member
I wish you luck teaching the harassment gangs some process technology :awe:
Intel engineers have generally been quite open and honest about what
they were doing and with good arguments. What the foundries are now
doing at 20nm-->14nm: Not scaling the MT1 half pitch is what Intel
already did at the 90nm-->65nm transition. Intel scaled the MT1 half
pitch only 5% from 110nm to 105nm.
Now when the rest of the industry is finally doing the same as Intel has
been doing since 2005 the fanboys are calling it a fake 14nm process..
The above is from a famous presentation of Yan Borodovsky:
"Marching to the beat of Moore's law" of 2006(!) where he explains
Intel's decision not to scale the MT1 (metal layer 1) and keep
scaling it less as the rest of the industry.
http://document.li/982u
The most difficult process step with the lowest k1 is the MT1
layer. By scaling it less it becomes easier to achieve a process-
node. By the time they had invented a new 1D SRAM cell layout
which they could scale even without scaling the MT1 half pitch.
This became one of the main motivators for Intel's deviation from
the International Technology Roadmap for Semiconductors which
the rest of the industry is following
http://www.itrs.net/Links/2012Winter/1205 Presentation/Lithography_12052012.pdf
I guess even showing Intel's own engineering presentations won't
change anything here. Every post with useful information is subsequently
buried in a stream of BS posts... 🙂
Hans
Last edited:
ancientarcher
Member
Every time there is a discussion, it turns into a shouting match as to how Intel's 14nm (or even 22nm) is superior to the TSMC/Common Platform's 16/14nm. But my dear friends, that is not what is important because Intel and the foundries compete on a very thin sliver of the market (FPGAs, what else?).
What is important is whether the improvement from 28nm to 14/16nm for the foundries will be significant. If you say that the foundries are lying on 14/16nm, they must surely be lying about 28nm as well. In which case, the improvement resulting from going to 14/16nm from 28nm is still the same if they had (in your opinion) told the truth.
The point is simple - the ARM ecosystem (including A7) is going to get 2 process node improvements in 2 years and Intel is going to receive just one. Now, you can argue all you want tills the cows come home about how TSMC/Common Platform guys are deluded that they can manage this. Your view! Just remember that Samsung/TSMC/IBM et al are not chimps, and Samsung is already doing <20nm in memory. so, it is not an idle boast. I know it is different from logic, but they do have the history of successful execution in semis. you can't dismiss them as easily as you did AMD.
What is important is whether the improvement from 28nm to 14/16nm for the foundries will be significant. If you say that the foundries are lying on 14/16nm, they must surely be lying about 28nm as well. In which case, the improvement resulting from going to 14/16nm from 28nm is still the same if they had (in your opinion) told the truth.
The point is simple - the ARM ecosystem (including A7) is going to get 2 process node improvements in 2 years and Intel is going to receive just one. Now, you can argue all you want tills the cows come home about how TSMC/Common Platform guys are deluded that they can manage this. Your view! Just remember that Samsung/TSMC/IBM et al are not chimps, and Samsung is already doing <20nm in memory. so, it is not an idle boast. I know it is different from logic, but they do have the history of successful execution in semis. you can't dismiss them as easily as you did AMD.
So you are counting the half-baked 14nm as a new node?
16/14nm is just a FinFET-enabled variation of their 20nm process, essentially.
It's all coming back to the fact that node labels are marketing terms -- a foundry could literally call their 20nm node a 16nm node the next, without doing anything at all. It's not really an accomplishment to launch two new nodes -- the accomplishment comes from the technological improvement. Do you get what I'm saying? Names and nodes don't mean much or anything at all -- it's the level of improvement that matters, and hopefully we get some sense of how big 20nm and 16/14nm will be at IEDM this year.
Samsung does have a good track record, though, and the less IBM has to say in their development, the better, it seems.
AtenRa
Lifer
Of course it is a new node, you get FinFets over planar with 14nm-XM.
It doesn't matter whether it's a new node or not. See my post above.
Yeah, that's a good point. Even if 16/14nm "counts" as a new node, two nodes in two years don't mean nearly as much when the first was so delayed.
AtenRa
Lifer
Im not talking about the naming, im talking about the physical(3D) and electrical characteristics of the 14nm-XM node vs 22/20nm node. They may use the 22/20nm BEOL but the FEOL for the 14nm-XM is a completely new process.
I wish you luck teaching the harassment gangs some process technology :awe:
Intel engineers have generally been quite open and honest about what
they were doing and with good arguments. What the foundries are now
doing at 20nm-->14nm: Not scaling the MT1 half pitch is what Intel
already did at the 90nm-->65nm transition. Intel scaled the MT1 half
pitch only 5% from 110nm to 105nm.
Now when the rest of the industry is finally doing the same as Intel has
been doing since 2005 the fanboys are calling it a fake 14nm process..
The above is from a famous presentation of Yan Borodovsky:
"Marching to the beat of Moore's law" of 2006(!) where he explains
Intel's decision not to scale the MT1 (metal layer 1) and keep
scaling it less as the rest of the industry.
http://document.li/982u
The most difficult process step with the lowest k1 is the MT1
layer. By scaling it less it becomes easier to achieve a process-
node. By the time they had invented a new 1D SRAM cell layout
which they could scale even without scaling the MT1 half pitch.
This became one of the main motivators for Intel's deviation from
the International Technology Roadmap for Semiconductors which
the rest of the industry is following
http://www.itrs.net/Links/2012Winter/1205 Presentation/Lithography_12052012.pdf
I guess even showing Intel's own engineering presentations won't
change anything here. Every post with useful information is subsequently
buried in a stream of BS posts... 🙂
Hans
Your timely post will not be lost on all of us. A few of us actually care about process technology rather than just treating it as a bullet point in an argument. I had no idea that Intel stopped decoupled scaling of the xtors and first metal layer @ 65nm. Makes sense, especially now, in terms of reducing resistance and parasitic capacitance while still increasing xtors/mm2 for each successive shrink. Thanks for a great post!
For simplicity sake, saying it's a new node is correct, because it is. But people should take your point seriously. What is gained by a new node in xtors/mm2 and electrostatics is, technically, the whole point of a new node. The benefits to the customer (internal or external) are all that matter - as far as node names go - they have to be called something; we just need to realize that those names don't have a real connection to reality.
The fact that you're still arguing about it shows that you've learned nothing from my post. What you're arguing about does not matter.
AtenRa
Lifer
It does matter because a new node brings substantial gains in density and electrical characteristics of the xtors than the older node. I dont see what the naming of the process, that you were talking about, has anything to do with the 14nm-XM is a new node over the 22/20nm.
Im not arguing about the naming and if it's corresponding to the Physical size of the xtors, im arguing if the 14nm-XM is a new node over the 22/20nm.
ShintaiDK
Lifer
Is 20nm vs 20nm with finfet a new node? Because thats pretty much how they add nodes this time around.
It's applicable to the "real node" vs. "not a real node" garbage as well. It doesn't matter whether or not it qualifies as a new node by definition -- the only way to assess that is by comparing published process specifications.
You're arguing semantics. It doesn't matter whether the node qualifies as a red node or a blue node. That goes for anyone else debating it as well.
For those interested in the process technology side that Cherrytrail is using, Intel provided a few more tidbits regarding their 14nm process today at their Analyst Meeting. http://intelstudios.edgesuite.net/im/2013/pdf/2013_IM_Holt.pdf
The status charts on page 4 should dispel any remaining notions that Intel isn't on track to produce 14nm chips according to their updated schedule. Then the switching energy versus gate delay charts (with exact comparisons on page 6) shows better characteristics going from 22nm to 14nm than they were claiming for 32nm to 22nm.
And lastly, to humor those who wish to cling to the fact that Intel density scaling hasn't quite been equal to the foundry competition for awhile, they provide their analysis on node density comparisons for current and future on page 11. As is already well-known, Intel's density is slightly lower on the 32nm vs 28nm and 22nm vs 20nm comparisons (and that would continue to 45nm and 65nm if they went furthure back, though at the same time Intel's transistor performance characteristics have trounced the competition on each of those nodes)... but come 14nm and 10nm they're projecting a marked density advantage.
The status charts on page 4 should dispel any remaining notions that Intel isn't on track to produce 14nm chips according to their updated schedule. Then the switching energy versus gate delay charts (with exact comparisons on page 6) shows better characteristics going from 22nm to 14nm than they were claiming for 32nm to 22nm.
And lastly, to humor those who wish to cling to the fact that Intel density scaling hasn't quite been equal to the foundry competition for awhile, they provide their analysis on node density comparisons for current and future on page 11. As is already well-known, Intel's density is slightly lower on the 32nm vs 28nm and 22nm vs 20nm comparisons (and that would continue to 45nm and 65nm if they went furthure back, though at the same time Intel's transistor performance characteristics have trounced the competition on each of those nodes)... but come 14nm and 10nm they're projecting a marked density advantage.
Interestingly, in that same presentation its projected that from 2013 to 2016 (I'm guessing from CloverTrail Z2760 to Broxton) we'll see a 5x improvement on the CPU side and 15x on GFX. CPU wise thats a current geekbench 3 score of 2150 for single-core (32 bit seems likely), not too bad for two years, it'll be interesting to see where Apple is with their A9, and the A57's from the other vendors.
SiliconWars
Platinum Member
Frankly I'd be terrified looking at that 14nm yield chart. Daniel Nenni was there and he has some more info.
https://www.semiwiki.com/forum/content/2954-qcom-delivers-first-tsmc-20nm-mobile-chips.html
Amusing as that's not what I heard in any of the material presented today - they were pretty clear about having 14nm SoCs in 2H 2014.
As for the yield chart, one point I didn't hear is whether that's with respect to the original or updated schedule. Since they have months on the X axis I'd presume that it's with respect to the original schedule. And while it still doesn't really look 'good' in that respect it provides the 'data' behind their claim that they are back on a normal track after having had roughly a quarter of no progress.
SiliconWars
Platinum Member
The problem I have with them making that forecast is that the history shows they take a step back for every one they take forward - even this month they had 3 drops. Right now it's only about equal to 22nm 6-9 months earlier.
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