Sorry HardwareAddicted, but guy at awaremag.com edited out the WRONG pins.
There are "two" Multiplier functions...FID[3:0} Multiplier "ID" which "identifies" multiplier info to the Northbridge for the system to initialize and set timings...and BP_FID[3:0] FSB Multiplier which actually sets the FSB Multiplier inside the cpu.
Both functions are connected to 4 socket pins each...FID to send multiplier info to the Northbridge...and BP_FID to allow connection to mobo dipsw's/jumpers to over-ride the default multiplier settings for oc'g.
You can't remove the FID pins, the system "needs the info". But AMD is "rumored " to be considering removing the BP_FID pins which would prevent mobo hardware from oc'g/changing default multiplier...just like the "open" L1 bridges tried to do.
awaremag.com was obviously "not aware" of all this, as they used the FID Multiplier 'ID" pins from pics, clearly labeled as FID, at Anand article and Dr Tom article. Check aware's links to those pics to verify.
BP_FID pins, in series with the L1 bridges, are along edge on left side of aware's pic, and you can find pics of labeled BP_FID pins at Anand and Dr Tom Duron OC articles. Even Anand was not initially aware of BP_FID pins because AMD did not document them...they hid them as undocumented pins...Marked NC for "no connection" on pinout diagram in Duron datasheet. We rang out L1 circuits and found them...first.
We also posted an "Alert Wrong Pins" thread here a few days ago.
http://members.xoom.com/candjac/index.htm for full oc'g details...all circuits.
John C.