I can get a celeron 1 gig for little if any money and I want to go dual with this, is this possible? and with what mainboard? I also want to spend as little as possible.
celeron 1ghz smp capable? what mobo?
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Confused
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- Nov 13, 2000
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All Celerons after the original PPGA (300-533MHz) are SMP locked, probably because Intel lost so much money on those original PPGA Celerons and the Abit BP6!
Even the standard P3s are SMP locked (i think), you have to get special SMP ones for that.
Confused
Even the standard P3s are SMP locked (i think), you have to get special SMP ones for that.
Confused
p3 tualatins are smp locked
you have to get the p3s tualatins with 512k L2 cache
i'm pretty sure only the dual capable ones have 512k L2
so all coppermine p3s are dual capable, p3 tualatins must be the dual capable high cache variant
you have to get the p3s tualatins with 512k L2 cache
i'm pretty sure only the dual capable ones have 512k L2
so all coppermine p3s are dual capable, p3 tualatins must be the dual capable high cache variant
As far as CUmine's working in SMP, it goes something like this:
The first implementaion was not SMP enabled as I recall, not the Katmai but the slot CUmine. The 'A' chip.
The B, C, and D stepping would all run in SMP with like steppings. Also, C would run with either B or D, but B and D were not compatible with one another. Katmai's were all SMP enabled, and Tualatin's are not.
On another note, I'm curious how much Intel actually 'lost' from not disabling the original celeron. Must of the adopters of BP6's probably went that route because of the cheap performance, and would not have otherwise even sprung for SMP, and 2 celerons was still more expensive than a single P2 of equal clockspeed. I think what they lost from corporate applications probably wasn't much, since I never saw any of the big server manufacturers marketing BP6 setups, and some gain was probably had from increased celeron sales. I ran celerons back then because of the sheer overclockablity and game performance due to the on die full speed cache. I owned a BP6 that is still running solid, and it was an inexpensive investment that I would otherwise not have owned were it not for the price. Now I own Dual Athlons, because I could never afford Xeons.
The first implementaion was not SMP enabled as I recall, not the Katmai but the slot CUmine. The 'A' chip.
The B, C, and D stepping would all run in SMP with like steppings. Also, C would run with either B or D, but B and D were not compatible with one another. Katmai's were all SMP enabled, and Tualatin's are not.
On another note, I'm curious how much Intel actually 'lost' from not disabling the original celeron. Must of the adopters of BP6's probably went that route because of the cheap performance, and would not have otherwise even sprung for SMP, and 2 celerons was still more expensive than a single P2 of equal clockspeed. I think what they lost from corporate applications probably wasn't much, since I never saw any of the big server manufacturers marketing BP6 setups, and some gain was probably had from increased celeron sales. I ran celerons back then because of the sheer overclockablity and game performance due to the on die full speed cache. I owned a BP6 that is still running solid, and it was an inexpensive investment that I would otherwise not have owned were it not for the price. Now I own Dual Athlons, because I could never afford Xeons.
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