Yup, it seems that you are right. I copied the excerpts from that article here:
"Like all SDRAM implementations, DDR2 stores memory in memory cells that are activated with the use of a clock signal to synchronize their operation with an external data bus. Like DDR before it, DDR2 cells transfer data both on the rising and falling edge of the clock (a technique called double pumping). The key difference between DDR and DDR2 is that in DDR2 the bus is clocked at twice the speed of the memory cells, so four words of data can be transferred per memory cell cycle. Thus, without speeding up the memory cells themselves, DDR2 can effectively operate at twice the bus speed of DDR."
The memory divider actually raises the 2x memory bus speed, e.g. 266MHz x 1.5 = 400MHz, which is already twice the memory bus speed of 200MHz.
It makes it confusing as hell for everyone, but based on the above it is correct.
Thanks, BitByBit.