Can this delidding catastrophe be salvaged?

[crashtech]

And cost. I don't mean cost of the TIM, but the cost of the solder (as in a BoM reduction) as well as the manufacturing cost.

Going to cost you a lot more money to put a CPU through the soldering step than the expense of putting it through a TIM step. No heating/melting/setting of the solder. The time involved, the cost of the facilities, plus QRA on soldered items is a lot more intensive than QRA on a silicon-based TIM pad.

There are lots of reasons, all expense related when it comes right down to it, that might have motivated Intel to transition from solder to TIM for their mainstream desktop SKUs.

But I disagree with the school of thought that would argue to say Intel intentionally made the transition because they wanted to gimp the OC'ing headroom on the mainstream "K" chips.

That may have been an unintended consequence of the decision to save a few more bucks from the BoM and manufacturing expense but I do not believe it was done out of malice or an intent to manipulate the enthusiast to up-sell them into a LGA2011 platform.

I don't disagree with this, but then how does one rationalize the excessive gap? An IHS with TIM application could be done with a far closer tolerance, imo, yet Intel chooses not to do so. Why?

 

[Idontcare]

I don't disagree with this, but then how does one rationalize the excessive gap? An IHS with TIM application could be done with a far closer tolerance, imo, yet Intel chooses not to do so. Why?

I see that as yet another trade-off in the "keep the manufacturing costs low". Tolerance costs you money.

You have to pay engineers to design a production system that can operate within the tigher tolerance (expense to be amortized across all units produced), you have to pay more per unit for the production line itself running slower as needed to hit the tolerance window (fixed expense directly added to each unit), you have to pay more for your QRA inspections to ensure the chips are actually coming out of the line within the intended tolerance, etc.

By giving themselves a nice sloppy-wide tolerance they have engineered into the product a lower cost manufacturing pathway. Some chips will have thinner TIM gaps than others, and it will all pass spec.

This is where TJmax and TDP come in. They are leveraging the superior process technology as a means of lowering production costs of the final unit because they can save money in the IHS loop knowing that up to a certain tolerance (TIM thickness) the chip will still be within spec in terms of operating temperature and power consumption.

If they needed to shoehorn a more power-hungry chip into a TJmax window that was even lower then they would not have the luxury of being able to trade-off the BoM and manufacturing expense for the higher thermals.

Its all about cost-management. Even the thermo-mechanical issues are cost-management. Intel can engineer a product that doesn't succumb to thermo-mechanical issues, but it would cost more.

So in choosing to not spend more per unit, in choosing to go with the less expensive means of isolating the CPU from the CTE mismatch between the IHS and the silicon die, they are in effect still making cost-benefits based decisions.

This is why I say the discussions on why Intel went with the TIM instead of the solder turn into red herring arguments because yes it is a technical issue, but all technical issues are just cost-based issues at the end of the day, but that isn't to say the decision was solely motivated on the basis of profit potential of upselling either (another red herring).

These are rational cost-benefits tradeoffs being made as a necessary balance between the technical issues and the accounting issues, which are just two-sides of the same coin in the end.

 

[crashtech]

I don't know if I accept that explanation, the TIM gap is way wider than it needs to be before assembling and measuring would have to be so precise as to add any appreciable cost. Seriously, it has to be by far the loosest tolerance in the whole assembly, by a wide margin.

But then again, in the last part of your post, with the mention of CTE mismatch, you essentially agree with my earlier post, which at first I thought you actually disagreed with. So now I question whether we disagree at all, and should just say "all of the above."

 

[Haserath]

I find it funny that a company that manufactures products with nm tolerances leaves a huge gap tolerance for their products as well.

 

[Idontcare]

I don't know if I accept that explanation, the TIM gap is way wider than it needs to be before assembling and measuring would have to be so precise as to add any appreciable cost. Seriously, it has to be by far the loosest tolerance in the whole assembly, by a wide margin.

But then again, in the last part of your post, with the mention of CTE mismatch, you essentially agree with my earlier post, which at first I thought you actually disagreed with. So now I question whether we disagree at all, and should just say "all of the above."

I've been talking about CTE mismatch in these forums ever since IB came out, so I absolutely agree with the technical possibility.

The problem still stands either way though, as you noted, which is that the gap itself is an order of magnitude larger than it need be even for the purpose of decoupling the lateral sheer stresses from CTE mismatch between the IHS and the die.

So, regardless the primary motivating reason why Intel went without the solder, the height of the gap itself remains unresolved to any degree of satisfaction.

I will say though, in passing observation of delidding a number of ICs (like my GPU, etc) the thick layer of TIM between the die and the underside of the IHS seems to be common practice and not something unique to Intel. What made it glaringly obvious with Intel was that we had our 32nm soldered SB's to compare to and that made it all the more painfully notable that the IB chips had a "less than optimal" thermal interface situation.

 

[Idontcare]

I find it funny that a company that manufactures products with nm tolerances leaves a huge gap tolerance for their products as well.

The farther away from the fab the product gets, the less money the people are resourced with to get their job done.

This is universal. Some of the tools used in packaging today are barely better than what was used in the 70's.

We had a "yield enhancement" trick at TI which was implemented to improve yields on our DLP chips (the micro-mirror chips) by some 20%...the "trick" was that we built a device that looked like a catapult which would firmly hold one wafer from the backside (vacuum held) and it would launch the wafer (face forward) in an arc just like a catapult. Only when the catapult arm got to the end of its travel it would slam into the arm-stops, exerting large g-forces on the wafer and in turn "fling" the particles off the front side of it.

Imagine if your best method for cleaning your windshield was to drive as fast as you could followed by slamming on the brakes to slow as quickly as possible, letting the debris on the windshield to fly off :hmm:

Not exactly high tech, not exactly tight on the tolerance, but effective enough to actually make it into a billion dollar production line as a standard piece of equipment for yield enhancement.

 

[Aikouka]

We had a "yield enhancement" trick at TI which was implemented to improve yields on our DLP chips (the micro-mirror chips) by some 20%...the "trick" was that we built a device that looked like a catapult which would firmly hold one wafer from the backside (vacuum held) and it would launch the wafer (face forward) in an arc just like a catapult. Only when the catapult arm got to the end of its travel it would slam into the arm-stops, exerting large g-forces on the wafer and in turn "fling" the particles off the front side of it.

Imagine if your best method for cleaning your windshield was to drive as fast as you could followed by slamming on the brakes to slow as quickly as possible, letting the debris on the windshield to fly off :hmm:

Not exactly high tech, not exactly tight on the tolerance, but effective enough to actually make it into a billion dollar production line as a standard piece of equipment for yield enhancement.

:hmm:

I guess I no longer need to wonder why the mirrors in my Samsung DLP started failing to flip back.

(Before someone chimes in. Yes, yes... moving parts fail. DLPs have tons of moving parts.)

 

[sm625]

Clearly that copper that you gouged was just a ground or power plane. The only thing you have to worry about is possibly damaging the insulator beneath that spot leadign to a short to the traces below. I'm sure there are traces below it because the chip is an LGA. But we have no way of knowing whether the traces are one layer below or 2, 3 or 4 layers below it. Or maybe there is another plane immediately below it.

Here is an example of an 18 layer board:

 

[crashtech]

@IDC, that is a hilarious story, and an illustrative insight!

 

[Haserath]

The farther away from the fab the product gets, the less money the people are resourced with to get their job done.

This is universal. Some of the tools used in packaging today are barely better than what was used in the 70's.

We had a "yield enhancement" trick at TI which was implemented to improve yields on our DLP chips (the micro-mirror chips) by some 20%...the "trick" was that we built a device that looked like a catapult which would firmly hold one wafer from the backside (vacuum held) and it would launch the wafer (face forward) in an arc just like a catapult. Only when the catapult arm got to the end of its travel it would slam into the arm-stops, exerting large g-forces on the wafer and in turn "fling" the particles off the front side of it.

Imagine if your best method for cleaning your windshield was to drive as fast as you could followed by slamming on the brakes to slow as quickly as possible, letting the debris on the windshield to fly off :hmm:

Not exactly high tech, not exactly tight on the tolerance, but effective enough to actually make it into a billion dollar production line as a standard piece of equipment for yield enhancement.

"What the hell just hit the side of our building?! "
"The process engineers are at it again."

The packaging does need quite a bit of finesse anyway, but it's just one of those 'they can do this but not this?' moments.

 

[aigomorla]

id like to add on top.

The OP reduced his overall temps by a STAGGERING 45-50C on load tables.

That means in a high workload enviorment... he has just effectively extended the working life on it by 32x intel's gaurentee'd point.
(every 10C reduced doubles. so 2x2x2x2x2 = 32x)
32x!!!!

:rofl:

So as long as there is no physical damage done... that cpu has a life of 3x32=96yrs!!!
(holy cow its like the newborns of this generation all having life expediency's of over 100)

lol im sure im wrong somewhere, because we play into material stress as well... but... mah....

Not exactly high tech, not exactly tight on the tolerance, but effective enough to actually make it into a billion dollar production line as a standard piece of equipment for yield enhancement.

but that gave u better yields... it probably also brought overall consumer cost on item down as well.
I remember TI stuff getting CHEAPER... not staying the same for less quality.

Intel not using solder is like the airline companies removing olives from salads...
Yeah they both saved... but both made the consumer not happy because we saw no reduction in price for a reduced quality.
If the savings trickle down to us consumers.. then by all means... GUT GUT GUT!!!
however if the savings are all absorbed on the corp end.. and they just cut quality out... it doesnt feel right in the stomache...
especially one that used to try hard to please even the smallest community of techies who went with intel products...

And intel did try to get out there to all communities... even the overclocking community when it was still emerging.
(Before MB vendors took over like Gig and ASUS hence why they are all now sponsored by the MB makers)

 

[Idontcare]

Intel not using solder is like the airline companies removing olives from salads...
Yeah they both saved... but both made the consumer not happy because we saw no reduction in price for a reduced quality.
If the savings trickle down to us consumers.. then by all means... GUT GUT GUT!!!
however if the savings are all absorbed on the corp end.. and they just cut quality out... it doesnt feel right in the stomache...
especially one that used to try hard to please even the smallest community of techies who went with intel products...

The alternative would have been for Intel to raise prices. They need to make an extra buck, they can either charge you that extra buck (which becomes an extra 10 bucks once the distribution chain does the standard mark-up thing) or they can reduce the BoM on their end by a buck and keep the prices the same.

Same with the olives. Did you want to see your airline ticket price increase $5 so the olives could stay in your salad, or are you OK with letting go of the olives and keeping the ticket at the same price?

I understand it is fashionable to vilify any business, or business person, who can be characterized as raising prices (baggage fees) or lowering cost/quality (there's no solder on ma CPU!) but how many of us expect to work year after year with zero adjustments to our salaries and wages?

Every single person here in this forum expects their bosses to pay them more money next year for doing the same job they did this year, but we refuse to extend the same allowance to our fellow humans because in them pursuing a raising wage for themselves that requires their employer to raise the prices charged to us when we buy their products.

It is a rather selfish perspective when you think about it. Wanting more for yourself while denying others the same.

 

[pmv]

Every single person here in this forum expects their bosses to pay them more money next year for doing the same job they did this year,

I'm not really disagreeing with the rest of your point, but this just isn't true these days. Perhaps it is in the US, but in Europe wages for all but the highest earners have been going down in real terms for several years now. It would be wildly optimistic to suddenly start expecting to be paid more now!

For UK:

The Institute for Fiscal Studies says workers have suffered unprecedented pay cuts of 6% in real terms over the last five years.

And I dread to think what its like in places like Greece.

Getting into P&N, sorry. But I just don't know anyone who 'expects' to be paid more next year!



I'm not disagreeing with the rest of your comment. Intel's decision over solder was entirely up to them. I guess it was just unfortunate for the small percentage of tech-obsessives and overclockers (who might, I suppose, given the choice, have rather paid a bit more for better heat dissipation), but commercially it presumably made sense for Intel with regard to the mass market and there's no reason for them to be bothered about the minority.

 

[aigomorla]

It is a rather selfish perspective when you think about it. Wanting more for yourself while denying others the same.

??? im lost IDC... ur telling me consumerism is a very selfish perspective? :biggrin:

however intel has increased volume.
they most likely have also reduced waste / increased yield efficiency.
Like you said at TI... catapulting a waffer netted greater yield which translated into billions.

Well im sure Intel has a Zero Point Module of some sort to tweak there yield on several processes to net them several billions.
we buy more chips... they produce better yields... we see savings to entice us to buy newer chips... repeat...
its been this model after c2d... and as yield got better and better, we been seeing the savings.

Celeron and Pentiums are CHEAP!!!

Intel when rushed/QC ignored/stressed makes oops / mistakes like the IHS.
(Launch of C2D!!! remember how some IHS were concaved IN)
They made this oops back then... back when AMD was gobbling Intel's control at an alarming rate.

After that, we havent had a IHS problem.. until... HASWELL.

Now we clearly see its a IHS gap problem, that leads me to couple of things.
1. Is intel really that stupid to miss a IHS gap problem? <-- whose running intel?
2. Does intel know about the IHS gap problem.. dont care cuz its in spec...doing it to save cost... <--- so then are they recycling old IHS which never got lidded?
3. Does intel just NOT care cuz its consumer HASWELL and the consumer doesnt require the extra QC so they push that consumer into enthusiast?
IVB-E is solddered... Cooler ripped the DIE right off his cpu pcb....

This is why im picking at Intel IDC.
To me its straight up... they didnt care... or they are recycling something and its not exactly fitting correctly... because we know for sure they arent stressed at AMD and it wasnt a rushed OOPS.

 

[MrPickins]

id like to add on top.

The OP reduced his overall temps by a STAGGERING 45-50C on load tables.

Look again, the "Before" temps were using the Intel stock cooler, the "After" with a Notcua NH-U14S.

Not exactly an apples to apples comparison.

 

[Idontcare]

Look again, the "Before" temps were using the Intel stock cooler, the "After" with a Notcua NH-U14S.

Not exactly an apples to apples comparison.

Yeah, from my tests I'd venture to say he got a 20C reduction from delidding and the remainder from the improved HSF.

Not a bad ROI for delidding considering that the 20-30C reduction he got from his U14S cost him a precious penny

 

[Kenmitch]

Good results! Kinda tainted by the cooler swapping tho. None the less worth the hassle it looks like.

Might just do my 4670k on my next day off. My chip is a good clocker but I lost the thermal lotto it looks like....At least for heavy hitting stress testing at least.

 

[JimmiG]

Definitely recommend the vice method. Much safer than blade. A friend did it with his Ivy Bridge with amazing results. We might have a go at my 4770K next week if I'm up for it. Those resistors are definitely a concern, but as long as you don't hit it from the side where they are closest to the seal it should be fine.

Good results! Kinda tainted by the cooler swapping tho. None the less worth the hassle it looks like.

Yeah I agree. Those pre-delid temps were just horrid. Mine's nowhere near that hot even at 4.3 GHz. Would have been interesting to see the temps with the Noctua before de-lid.

Beyond the lidding issues however, the chip has limited ability to be overclocked, from what I am reading. That is, the voltage you have to apply past a certain level of overclocking exponentially increases the heat. Someone correct me if I have this wrong.

That is my main concern as well. If the CPU runs 20C cooler, that's great. However if after adding another 100 MHz to the OC, the voltage required goes through the roof, there's really no point. I can't really test that at this point, because anything over 1.25V causes temps to go totally out of control. However with a de-lid, 1.3V and beyond should be possible.

 

[Kenmitch]

That is my main concern as well. If the CPU runs 20C cooler, that's great. However if after adding another 100 MHz to the OC, the voltage required goes through the roof, there's really no point. I can't really test that at this point, because anything over 1.25V causes temps to go totally out of control. However with a de-lid, 1.3V and beyond should be possible.

They do tend to run on the hot side at times. Pitty those with the stock cooler.

I'm currently testing mine at 4375MHz (35x125) 1.183v's (fixed) using a H100i on balanced setting. Using the 1.25x I can overclock my memory to 2000MHz also.

I'm currently using AIDA64 stress test with cpu, fpu, cache, memory (2g per thread)

2hr20min into it so far and temps are reasonable at least. Package temp max of 71c

I've had my chip up to 4.8ghz so far with stability maybe....Reason I say maybe is it gets throttled by the hard hitters like IBT, etc. Crazy temps once cranked up.

The nerd in me wants to delid, my wallet says you'll be sorry if the F it up. Looks easy enough tho if one is careful.

 

[wilds]

These temperature reductions are extreme. Intel should have spotted this because the benefits definitely outweigh the cost reductions and negative PR.

 

[JimmiG]

They do tend to run on the hot side at times. Pitty those with the stock cooler.

I'm currently testing mine at 4375MHz (35x125) 1.183v's (fixed) using a H100i on balanced setting. Using the 1.25x I can overclock my memory to 2000MHz also.

I'm currently using AIDA64 stress test with cpu, fpu, cache, memory (2g per thread)

2hr20min into it so far and temps are reasonable at least. Package temp max of 71c

I've had my chip up to 4.8ghz so far with stability maybe....Reason I say maybe is it gets throttled by the hard hitters like IBT, etc. Crazy temps once cranked up.

The nerd in me wants to delid, my wallet says you'll be sorry if the F it up. Looks easy enough tho if one is careful.

You really need to run with only FPU checked to stress the cooler. With all four checked, my cores peak at 74C (except the worst core which goes to 76C). That's with HT enabled as well which increases temps. CPU package tops out at 64C.

It's really only the FPU test and Linpack (especially the AVX 2.0 version) that increases my temps to the edge of throttling. If it wasn't for them, I could easily run at 4.5+ GHz.

 

[Idontcare]

These temperature reductions are extreme. Intel should have spotted this because the benefits definitely outweigh the cost reductions and negative PR.

These temperature reductions are for overclocked chips, not stock.

 

[Kenmitch]

You really need to run with only FPU checked to stress the cooler. With all four checked, my cores peak at 74C (except the worst core which goes to 76C). That's with HT enabled as well which increases temps. CPU package tops out at 64C.

It's really only the FPU test and Linpack (especially the AVX 2.0 version) that increases my temps to the edge of throttling. If it wasn't for them, I could easily run at 4.5+ GHz.

Did you delid your chip?

Trying the AIDA64 FPU only at 4.5ghz 1.25v currently. Temps still reasonable with package peaking at 77c at the 20min mark, 40 min mark holding at 77c highest package temp....Shuts down and goes to work.

 

[DigDog]

incidentally, how does a delidded 4770k compare to a delidded 2500k? ermmm .. let me rephrase that.

the difference in OC room between lid-on / lid-off, is it much greater on haswell than it is on SB?
Did Intel make a chip (Haswell) which is a real improvement over SB, but then fucked up with the TIM / lid ?

 

[JimmiG]

Did you delid your chip?

Trying the AIDA64 FPU only at 4.5ghz 1.25v currently. Temps still reasonable with package peaking at 77c at the 20min mark, 40 min mark holding at 77c highest package temp....Shuts down and goes to work.

No, but maybe next week if I can summon the courage

What about the individual core temps? You can check the maximum recorded temps in the Statistics page in Aida64. Cores will be at least 10-15C higher than package.

I believe Tcase (maximum temp allowed for the package) is 72C.