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Can someone tell me what these BIOS settings mean?

J

John

Moderator Emeritus<br>Elite Member
I now have a question concerning the BIOS settings on the Asus P3V4X.

1) What does CPU-DRAM back-back transaction mean? should it be enabled or disabled?

2) What is Byte merge? should it be enabled or disabled?

3) What is PCI to DRAM Prefetch? should it be enabled or disabled?

4) What is DRAM read latch delay? what should it be set to (0.0, 0.5, 1.0, 1.5)?

5) What is Read around Write? should it be enabled or disabled?

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Guys when I slapped my P3V4X in last week I noticed my Pioneer 303s SCSI DVD seemed a lot slower (access times, installing programs) than when I had it on my BXMaster. I tried the latest Adaptec 2940uw driver and that didn't seem to help.

Any thoughts?

Has anoyone else had a similar issue?


 
I got the same drive on a Adaptec 2940U2W with a P3V4X. I havent noticed any bad performance with this setup at all. I'd say that it isnt set up correctly or the drive has gone bad. I need to RMA mine soon as it tends to click a bit.
 
any ideas on how you think &quot;it isn't set up correctly&quot;?

1005 bios on the p3v4x, 4.23 4-in-1's, latest adaptec 2940uw win2k driver, terminated scsi
 

Byte Merge Support. 8- or 16-bit data en route from the CPU to the PCI bus is held in a buffer where it is accumulated, or merged, into 32-bit data, giving faster performance. In this case, enabling means that CPU-PCI writes are buffered (Award).
 

PCI IDE Prefetch Buffers. Disables a set of prefetch buffers in the PCI IDE controller. You may need to do this with an operating system (like NT) that doesn't use the BIOS to access the hard disk and doesn't disable interrupts when completing a programmed I/O operation. Disabling also prevents errors with faulty PCI-IDE interface chips that can corrupt data on the hard disk (with true 32-bit operating systems).
 

CPU to PCI burst memory write. If enabled, back-to-back sequential CPU memory write cycles to PCI are translated to PCI burst memory write cycles. Otherwise, each single write to PCI will have an associated FRAME# sequence. Enabled is best for performance, but some non-standard PCI cards (e.g. VGA) may have problems.

Note: these items are CPU to PCI, but logic also applies to CPU to DRAM
 
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