Most CPU architectures are pipelined and superscalar now, so it can issue multiple instructions per clock cycle. For example, the Athlon can issue up to 3 integer operations per clock cycle.
Generally a CPU reads instructions from memory, executes them and stores the result of the operation back in memory. In a pipelined processor, there are 5 basic pipeline stages that an instruction has to go through before it is completed. These are the Fetch, Decode, Execute, Memory and Writeback stages. Each new clock cycle, any particular in-flight instruction will either proceed on to the next pipeline stage, or gets flushed out due to some kind of exception.
In the fetch stage, the CPU reads an instruction from memory into the instruction register. The CPU knows which memory address to read from based on the Program Counter(PC) which points to the next memory address to read.
In the Decode stage, the CPU dissects the instruction to figure out what operation it is and what operands it uses. It stores the operation and operands into separate registers.
In the Execute stage, the CPU takes the operands and operation and passes it through the ALU, in which the result is obtained.
In the Memory stage, the CPU accesses memory if the operation was a memory operation(Load/Store).
In the Writeback stage, the CPU stores the final result of the instruction into the appropriate register.
This is a very general view of the instruction lifecycle. Complications arise from stuff such as branch prediction, dynamic scheduling(OOE), register renaming and superscalar execution. It'll take more than a BBS thread to explain the intricacies. Good books to read regarding CPU architecture/ISA would be Computer Organization or Computer Architecture by Patterson & Hennessy. The former gives a broad overview while the latter covers more advanced topics.
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