TuxDave, I respectfully simply do not agree.
You have a preconception about this which no amount of my attempting to teach you is going to reverse. I recognized this earlier which is why I stated the sub-topic reach pointless proportions above.
Regarding:
As I mentioned elsewhere in other discussions on this same topic, having been directly involved with the ITRS committees, including discussions related to the drafting of this position on node labels, all I can attempt to do is communicate the spirit of the message.
But as I stated above, I've exhausted all the usual options and examples I iterate thru when this discussion comes up, as it has repeatedly for the past decade. There are some folks who are eager to learn, and others who are eager to defend what they have spent their careers assuming to be true. Having spent the time I did being involved in creating nodes firsthand I have informations I know to be true that I attempt to educate others about. But not everyone wants to hear what I have to say, and I am OK with that.
There are things I know to be true and then there are things I assume/believe to be true. This topic falls under the category of something I know firsthand to be true. I can't convince you with concrete evidence unless you were to take the R&D job of process development engineer or process integration and experience the decision making processes that go into node definition and creation firsthand.
All I can do is provide you with the socratic method style questions to assist you in unlearning that which you believe to be true. Your statement I quoted at the very top of this post is flat-out wrong, but how I can I prove it? I can't, no more than I can prove gravity will still exist tomorrow.
The top of the gate in product is not the drawn length, there is a resist trim process used. Per Intel's IEDM 2007 presentations the min Lg for the 45nm node is 35nm, the same as was used for the 65nm node.
The diffusion region is called the channel, the channel length is not the same as the gate length and usually it is only electrically characterized/defined and not physically as there is a gradation to the channel's dopant levels (S/D extensions and HALO) which make hard boundary definitions impossible and entirely arbitrary.
TuxDave
Lifer
- Oct 8, 2002
- 10,571
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Are you purposely trying to deter discussion by treating me as "unteachable"? I'm actively listening but if you keep starting off these conversations with "there's no way to teach you this" or "you are so set in your current knowledge it's impossible to change your mind" when I haven't stated any stubborness in my opinions but just instead offered my opinions with your opportunity to dispute. I'm mean seriously, this is a pretty screwed up way to treat a person you know nothing about.
I'm not quite sure what the socratic method is but let me offer you a very easy and straightforward approach. A circuit designer working on a 90nm process will have the drawn gate length listed (using their design ruler) as 90nm in their design tool. So to him, it appears that the 90nm label reflects something physical.
So how to prove your point? Tell me that the scale of devices and features that the circuit designer sees is pretty much meaningless and so the importance of the process label for marketing purposes extends down to the engineers themselves.
I cannot comment on stuff down to 45nm and 32nm but I do open the opportunity that once I start seeing large differences between the ldrawn and the process label it gives, then I'll agree that the process label is merely a marketing ploy but I just haven't seen it yet.
That's not what I am saying at all. I am saying I personally, as in me, have exhausted all the ways I know how to teach a person about this specific topic. The issue here is me, not you.
I know one thing based on experience and direct knowledge but I have failed, repeatedly, to effectively communicate this information to you in a way that invites its digestion, contemplation and critical assessment to the degree I was hoping to inspire at the outset of this lengthy discussion.
The failure to teach falls on the teacher, hence the specific reference to myself when I say "no amount of my attempting to teach you...". I lack the ability to effective communicate the information, clearly, and I have nothing left in the toolbox here so what I am going to do? Recycle the same examples, rehash the same tired statements that I went thru earlier in the thread? How is that going to be of any help to you?
If I was rash to jump to conclusions regarding your disposition on the topic then I do apologize, no I do not treat people the way you describe me as having treated you nor was I intending to give you that impression or feeling in making the statements I made.
FWIW Socratic method is essentially the art of intentionally asking rhetorical questions (i.e. the teacher knows the answer already) crafted in such a way and sequenced in such a way that the student walks themselves straight into a self-generated epiphany by answering the questions.
All my questions above in this thread were rhetorical in nature, they were not asked of you out of ignorance on my part regarding the answer. It was my hope that by you generating the answers to the questions, which I expected you to already know too, you would experience an enlightenment firsthand, by critically challenging the assumptions you have regarding what you think you know about node labels.
If you are talking about Intel's 90nm design rules then I cannot tell you why the inhouse layout tools are restricted to 90nm Lg. The min Lg for Intel's 90nm technology node is 45nm.
http://www.realworldtech.com/p...ID=RWT011608222300&p=6
Perhaps your particular product manager has restricted the allowed library in such a way that precludes you from accessing the smaller sized xtors in that node? I can only guess at explanations for your observations. Even for the same node, min Lg varies by company as well as application. Looking for stuff in the public domain to illustrate this...checkout slide 5 of this NEC litho workshop presentation as well as the assembled data in the RWT table I linked above.
TuxDave
Lifer
- Oct 8, 2002
- 10,571
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Thanks for clearing that up.
I'm referring to an ST Micro 90nm process which my University was allowed to work on 4 years ago. It was a dual oxide process of 90nm and 130nm where depending on where I was working on, the poly was measured at 90nm and 130nm. I kind of have to keep Intel stuff out of this conversation out of sheer ignorance of what is secret and what is not.
So on the NEC presentation: If we look at the 90nm process where there's to gate lengths available (fast and low leakage). I have seen this done where there's a minimal gate length and a slightly larger gate length for low leakage devices. I wish they would show where they are measuring their "physical gate length" though.
If I asked NEC to draw just a vertical grid of high speed poly and another a grid of low leakage poly, which would have a higher lines per um density? The lg makes it look like the high speed should be able to pack in more but the traditional understanding (where the packing is limited by the ldrawn which could be the same for both types of transistors) that would imply equal lines per um.
I'm referring to an ST Micro 90nm process which my University was allowed to work on 4 years ago. It was a dual oxide process of 90nm and 130nm where depending on where I was working on, the poly was measured at 90nm and 130nm. I kind of have to keep Intel stuff out of this conversation out of sheer ignorance of what is secret and what is not.
So on the NEC presentation: If we look at the 90nm process where there's to gate lengths available (fast and low leakage). I have seen this done where there's a minimal gate length and a slightly larger gate length for low leakage devices. I wish they would show where they are measuring their "physical gate length" though.
If I asked NEC to draw just a vertical grid of high speed poly and another a grid of low leakage poly, which would have a higher lines per um density? The lg makes it look like the high speed should be able to pack in more but the traditional understanding (where the packing is limited by the ldrawn which could be the same for both types of transistors) that would imply equal lines per um.
wow I learned a lot in this thread, So given that 45nm is just a label (as idontcare has repeated many times) this means it is possible for Intels "45nm" process to have transistors packed to twice the areal density of GF's "45nm process. So even though both processes appear to have equal density's it is still possible for (for instance) one "32nm" process to have a massive areal advantage over the competitors "32nm" process. It also means that I now also have no clue as to whether or not TSMC'c 40nm process has greater areal density than GF or Intel 45nm processes... weird.
Ahhhhhh after more reading I think I see the light! Please correct me if I am wrong here goes...
back in the day a shrink in gate length corresponded very accurately to a shrink in the whole transistor, thus if you reduce gate length by 1 - (SQRT2)/2 (or 29.3%) you will double the areal density of the chip.
Now however gate length does not correspond so directly to areal density SO............. when a firm doubles the areal density of a process they simply say that it is a "~30% smaller node" (65nm, 45nm etc.) even though that number does not correspond directly to any specific feature on the chip. It DOES however still IMPLY that the chips areal density has been improved in proportion to the reduction of the node label (so TSMC's 40nm process does have transistors packed tighter than Intel or GF's 45nm processes).
OK please don't bite.
back in the day a shrink in gate length corresponded very accurately to a shrink in the whole transistor, thus if you reduce gate length by 1 - (SQRT2)/2 (or 29.3%) you will double the areal density of the chip.
Now however gate length does not correspond so directly to areal density SO............. when a firm doubles the areal density of a process they simply say that it is a "~30% smaller node" (65nm, 45nm etc.) even though that number does not correspond directly to any specific feature on the chip. It DOES however still IMPLY that the chips areal density has been improved in proportion to the reduction of the node label (so TSMC's 40nm process does have transistors packed tighter than Intel or GF's 45nm processes).
OK please don't bite.
Those are pretty good extensions on the topic deputc26 :thumbsup:
First, you are hitting the nail on the head here. Armed with no more information than simply the node label (45nm, 40nm, etc) you have virtually nothing to go on for comparing two or more company's nodes.
What you have to go on is the expectation that when a company iterates their own node then that companies circuits are now smaller on the new node, sram cellsize is 50% smaller and most circuits can be 70% smaller in linear shrink.
Can be does not mean will be. Cost and performance considerations are tradeoffs at the design level and when power consumption is factored in it can result in optimal shrink factors that utilize slightly longer/wider transistors and less than minimum pitch features.
It is because of this influence from design in optimizing chips that we can't really make much effective comparisons between two company's transistor density unless we are lucky and the exact same chip architecture is implemented in both company's nodes.
Even sram cellsize comparisons are mostly meaningless between companies because they tend to lack the needed "circuit quality" data that goes along with the physical dimension data. For example at TI our marketing guys loved to tout the fact we had the smallest production sram at every node for some 4 or 5 nodes in a row...but this sram was weak (low clockspeed) and really was no comparison to the performance capability of Intel's sram at the same node even though their sram was larger than ours.
So to compare sram in a meaningful way between two company's (or even within the same company across more than one node or some such) you need some operational characteristic data as well - operating voltage (and range), clockspeed (shmoo plot), power consumption.
And even in the case where you get your hands on all that info it still doesn't speak to manufacturing costs - cycle time and yields in addition to direct costs resulting from process technology. Immersion litho versus double-patterning is a prime example of this tradeoff.
One comment regarding TSMC's 40nm - it is their 45nm node but they shuffled the node lable down to the half-node label to avoid the PR disaster of releasing their 45nm node 2 yrs behind schedule. See http://forums.anandtech.com/me...301315&highlight_key=y
TSMC now considers the 40nm node their "full" node (not the half node) and 32nm will be the half-node, and likewise the 28nm node will be described as a full node now whereas prior to 45nm cancellation it was intended to be described as a half-node. Now TSMC didn't actually cancel anything, what they cancelled was labeling their 45nm node as the 45nm node, what was going to be called 45nm node is now called the 40nm node. It makes for great marketing, which is pretty much the sole purpose of node labels anyways.
No one in the consumer world talks about what generation of LCD technology their TV is made from, nor do they talk about the generation of manufacturing technology used at the car manufacturing plant their minivan came from. But for CPU's it is an ingrained metric of marketing so we live with it.
First, you are hitting the nail on the head here. Armed with no more information than simply the node label (45nm, 40nm, etc) you have virtually nothing to go on for comparing two or more company's nodes.
What you have to go on is the expectation that when a company iterates their own node then that companies circuits are now smaller on the new node, sram cellsize is 50% smaller and most circuits can be 70% smaller in linear shrink.
Can be does not mean will be. Cost and performance considerations are tradeoffs at the design level and when power consumption is factored in it can result in optimal shrink factors that utilize slightly longer/wider transistors and less than minimum pitch features.
It is because of this influence from design in optimizing chips that we can't really make much effective comparisons between two company's transistor density unless we are lucky and the exact same chip architecture is implemented in both company's nodes.
Even sram cellsize comparisons are mostly meaningless between companies because they tend to lack the needed "circuit quality" data that goes along with the physical dimension data. For example at TI our marketing guys loved to tout the fact we had the smallest production sram at every node for some 4 or 5 nodes in a row...but this sram was weak (low clockspeed) and really was no comparison to the performance capability of Intel's sram at the same node even though their sram was larger than ours.
So to compare sram in a meaningful way between two company's (or even within the same company across more than one node or some such) you need some operational characteristic data as well - operating voltage (and range), clockspeed (shmoo plot), power consumption.
And even in the case where you get your hands on all that info it still doesn't speak to manufacturing costs - cycle time and yields in addition to direct costs resulting from process technology. Immersion litho versus double-patterning is a prime example of this tradeoff.
One comment regarding TSMC's 40nm - it is their 45nm node but they shuffled the node lable down to the half-node label to avoid the PR disaster of releasing their 45nm node 2 yrs behind schedule. See http://forums.anandtech.com/me...301315&highlight_key=y
TSMC now considers the 40nm node their "full" node (not the half node) and 32nm will be the half-node, and likewise the 28nm node will be described as a full node now whereas prior to 45nm cancellation it was intended to be described as a half-node. Now TSMC didn't actually cancel anything, what they cancelled was labeling their 45nm node as the 45nm node, what was going to be called 45nm node is now called the 40nm node. It makes for great marketing, which is pretty much the sole purpose of node labels anyways.
No one in the consumer world talks about what generation of LCD technology their TV is made from, nor do they talk about the generation of manufacturing technology used at the car manufacturing plant their minivan came from. But for CPU's it is an ingrained metric of marketing so we live with it.
The publicly disclosed Intel stuff, as listed in the process technology comparison table I linked to, is obviously not Intel Confidential so I think we can use this publicly stated information regarding Intel's Lg's here in this conversation.
As to ST Micro's 90nm and 130nm process tech...your access was not from within the company, again I am simply speculating here, but if I were ST Micro and I had Lg of 80nm on 130nm node and Lg of 60nm on 90nm node I would see no reason to enable academia to have access to the absolute best my process technology has to offer. What value would that bring to ST Micro and its shareholders? Restricting outside access to just the bare minimum Lg for a node kinda makes sense, but I fully acknowledge I am merely speculating here and I do not readily have access to the publicly documented min Lg's for ST Micro.
But even if ST Micro did not hold any cards close to their chest in this example you provide I can only say ST Micro was a primary competitor to TI at those nodes and the chips ST Micro put into the market place most certainly had Lg's that were smaller than those you list. Do you know how large their sram cells would have to be to accommodate a min Lg of 90nm on the 90nm node? Massive and uncompetitive. Sram scaling trend versus Node (chipworks blog) The TI sram there at 90nm was right at 1um^2 and that required a min Lg of about 55nm.
On the NEC...are you interested in uncontacted poly or contacted poly when discussing min-pitch for the gates/contacts? But yes I agree if NEC was single-pass printing (no fancy double-patterning) and they were printing the gate for both types of xtors at the absolute functional/practical limit of their litho equip then the uncontacted gate pitch would be the same in the question you pose. But that has little to do with comparing the gate pitch in contacted poly in functional IC's where contact pitch must be accounted for and contact leakage is a real problem from overlay and alignment metrics. It's really a complicated balance of engineering as you can well imagine given that it takes about 4yrs to make it work well enough to produce sellable product.
TuxDave
Lifer
- Oct 8, 2002
- 10,571
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It's possible but we essentially piggy backed off their process "almost" for free. Basically during any of their low volume tape ins, if there was room on their mask that they had nothing else to put in, they would allow academia to put their patterns in and then cut out the chips for us. I think we had to wait for about 3 tape ins before we finally got our designs in but who's to say that the internal usage of that particular wafer was limited. I'm just speculating now and it's probably impossible to ever know now.
I could probably work out the math assuming some made up 90nm process to compare with how much I would "expect" it to be vs what it actually was. But yeah that may take some memory jogging to figure out theoretically what it would be given some made up parameters of poly spacing, contact spacing, etc...
I bowed out of the thread (and the interent in general) due to a bout with something that felt suspiciously like the flu (fever finally went down last night). Feeling slightly better today.
Onto densities, I noticed Wikipedia's 45nm page had quite a few quotes about 6 transistor SRAM densities ( http://en.wikipedia.org/wiki/45nm ) most of which have references.
In 2004, TSMC demonstrated a 0.296 square micrometer 45 nm SRAM cell. In 2008, TSMC moved on to a "40 nm" process [with an SRAM cell size of 0.242um^2].
In January 2006, Intel demonstrated a 0.346 square micrometers 45 nm node SRAM cell.
In April 2006, AMD demonstrated a 0.370 square micrometer 45 nm SRAM cell.
In June 2006, Texas Instruments debuted a 0.24 square micrometer 45 nm SRAM cell, with the help of immersion lithography.
In November 2006, UMC announced that it had developed a 45 nm SRAM chip with a cell size of less than 0.25 square micrometer using immersion lithography and low-k dielectrics.
stuff in "[]" brackets added by me.
It's interesting to see what a huge difference immersion litho makes in terms of SRAM cell sizes.
My own take on the underwhelming 65nm performance for AMD is that their CTI protocol (Continuous Transistor Improvement) basically "robbed" all the 65nm xtor performance enhancement features as they were developed (so 90nm kept micro-iterating to higher and higher performance) such that by the time 65nm itself finally debuted all it effectively brought to the table above and beyond 90nm at that point in time was the areal shrink factor (which yielded some performance benefits) afforded by the tighter BEOL pitches.
(this is a very generalized simplistic view of the complex nature of process integration and development, I'm not saying the xtors used in the last production days of 90nm were identical to those used at that time in 65nm, although there was a publicly stated policy of STT - shared transistor technology - that paralleled CTI, but I'm painting with a broad brush here because I think the spirit of the point I am making is true)
There was a great slide presentation I saw recently (cannot for the life of me find it again) which showed the various xtor improvements made to 90nm via CTI up to the point that 65nm was released.
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