# Calculating how many atoms wide the X nm value of a CPU refers to

#### taltamir

##### Lifer
I looked up the silicon-silicon bond length, and it is 0.2352 nm wide.
A quick division then leads to interesting results.

For example: 40nm processor would have circuits that are 40 / 0.2352 = Si 170 atoms wide.

32nm / 0.2352 = 136 atoms wide.

Interestingly enough, there is a technology called strained silicon:
http://en.wikipedia.org/wiki/Strained_silicon

I am curious to know how much it increases the bond length, as my current figures are likely too high due to not taking straining into account.

#### TuxDave

##### Lifer
While we're at it, you should look up the data on the oxide thickness on those processes

#### Idontcare

##### Elite Member
Take a look at slides 6 and 7 of this UC Berkeley presentation on intro to semiconductors.

You need to account for the fact that silicon has a unit cell which is not simple cubic, and for the fact that semiconductors use different crystal planes (changes the areal packing density of silicon, relevant to your topic).

Also your dimensionality will be off if you equate the node label (40nm, 32nm, etc) with the physical dimensions of an underlying component such as the channel length (Lg) as you have in your OP. For 40nm the smallest Lg will be ~20-22nm and for 32nm the Lg will be around ~16-18nm (it varies by company of course).

Since you mention strained silicon, the current implementations of strained silicon do not significantly alter the unit cell dimensions of silicon. Currently the max cellsize changes are less than 1.5%. A strain of about 1% results in a stress of around 1.5GPa, going above 3GPa of stress results in prolific dislocations, so it is unlikely that we will ever see stress engineering cause significant dimensionality changes to the xtor.

#### taltamir

##### Lifer
thank you for the info. I will look into those and see about amending my calculations.

You are also more then welcome to do so and post it here if you are interested.

You mention channel length Lg being smaller than node label. What does not label stand for than?

#### Idontcare

##### Elite Member
Originally posted by: taltamir
You mention channel length Lg being smaller than node label. What does not label stand for than?

It's like "class" in auto's when folks advertise "JD Power and associates ranked best in class"...no two semiconductor companies 45nm or 40nm or 32nm process technologies will be same for any feature in the circuit, but they are lumped together as being in the same "class" or node label.

They could call them the Apple node and the Banana node for all the node label is worth. Long ago, back in the 1um and 0.5um days the node label was related to width of the gate (not the same thing as the channel). Nowadays it's just a label meant to imply the technology has iterated. Its not meant to be a mathematical measurement of anything. Phenom II is "2 x Phenom".

#### pm

##### Elite Member Mobile Devices
Originally posted by: Idontcare
Nowadays it's just a label meant to imply the technology has iterated. Its not meant to be a mathematical measurement of anything.

I understand the difference between Leff and Ldrawn but to say that process technology nodes are just a label without it being a measure of anything is a bit farther than I would go. SRAM cell size has decreased by approximately ~50% from generation to generation for as far back as I've been in the industry. The percentages bounce around from generation to generation, but the overall trend is for a 50% reduction. Decreasing SRAM cell size implies that the primary drawn features are getting ~30% smaller. And clearly if things are getting smaller on a consistent basis, then there is something measureable being reduced.

#### Idontcare

##### Elite Member
Originally posted by: pm
Originally posted by: Idontcare
Nowadays it's just a label meant to imply the technology has iterated. Its not meant to be a mathematical measurement of anything.

I understand the difference between Leff and Ldrawn but to say that process technology nodes are just a label without it being a measure of anything is a bit farther than I would go. SRAM cell size has decreased by approximately ~50% from generation to generation for as far back as I've been in the industry. The percentages bounce around from generation to generation, but the overall trend is for a 50% reduction. Decreasing SRAM cell size implies that the primary drawn features are getting ~30% smaller. And clearly if things are getting smaller on a consistent basis, then there is something measureable being reduced.

I think I know you well enough to know you don't mean to do it intentionally, but you've made a strawman argument there in that you are asserting that because successive nodes do deliver consistent improvements in their deliverables (sram density, etc) over past nodes and because surely there are physically measurable features within a given process technology (all of which is true, but I have not said any of this is untrue) that somehow this is to be invoked as proof that my assertion is untrue regarding node labels being simply labels.

I make the statement based on being right there in the decision rooms as new process technology nodes (something that already existed on paper as a label) had virtually every single physical and electrical attribute jockied around for yield/manufacturability reasons as well as risk to timeline and development cost. There is zero influence on these decisions stemming from the label given to the node.

We called the successor to the 45nm node as being the 32nm node for simple sake of the fact that is what marketing and media expected us to call the successor to our 45nm node. Had we used a different label then it would have appeared we were diverging from the rest of the industry.

Every car manufacturer associates their cars to a model year, even though the car itself may not have been manufactured in that year. My 2005 minivan was manufactured in 2004, but it is labeled as being a 2005 Toyota Sienna. Imagine if Toyota said next year they were going to label their cars by HP or MPG instead of the conceptually satisfying and naturally iterative labeling system that "model year" provides?

When a new node's specs are being "fleshed out" there is absolutely zero decision making going on to the tune of "well guys, this is going to be called the 32nm node so that means first and foremost we need 1/2 gate pitch to be 32nm" or "this is going to be called the 32nm node so that means first and foremost we need printed gate length, Ldrawn, to be 32nm".

There are design targets, i.e. deliverables, for a new node...50% areal reduction of some token circuit of merit (sram for some), 5x decrease in leakage, 20% increase in Idrive, etc. They are all based on successive iterative improvements from a pre-existing node or pre-existing specs for a node under development (N+1 vs N+2), etc.

There is a reason Intel internally refers to their 32nm node as the P1268 and 22nm as the P1270. Whether you call it 32nm or P1268, both descriptors are merely labels to differentiate the underlying process tech from prior and successive generations. And if I wanted to make false (and silly) maths with those labels to say silly stuff like ratios between them I could do things like say "CPU's on 22nm will be 22/32 = 69% the size of 32nm chips"...this is wronger than wrong, but no less correct than if I said "CPU's on P1270 will be P1268/P1270 = 99.8% the size of P1268 chips". In both cases I am treating a node label, a text item not a mathematical quantity, as if it were indeed a mathematical quantity which I can do maths with.

At TI we referred to them as C010 and C007 for 32nm and 22nm respectively. The numbers after the "C" (which itself stood for CMOS) did relate to a physical dimension of the process technology, specifically the M1 pitch. 100nm M1 pitch for 32nm node, and 70nm for 22nm node. But even these pitches were subject to change as needed to meet the deliverables. Our 65nm node for instance was internally called C021 implying a M1 pitch of 210nm...but about 18 months into development we realized we needed tighter pitch to deliver entitlement performance so we shrunk it further to 200nm, and then again to ultimately be 180nm for final device specs at manufacturing.

You making the argument that since things get smaller on a consistent basis (aka node reduction results in step-wise linear changes in deliverables) has nothing to do with what I am saying about the node label being nothing more than simply a label.

Did you know the ITRS dropped the effort to define a "node" altogether? I was there for the debates and attempts to keep it alive. The very concept of a node is something that lives on as a convenient terminology and concept.

edit: edited this post to update the quote of pm's post after his edits

#### pm

##### Elite Member Mobile Devices
Originally posted by: Idontcare
Originally posted by: pm
Originally posted by: Idontcare
Nowadays it's just a label meant to imply the technology has iterated. Its not meant to be a mathematical measurement of anything.

I understand the difference between Leff and Ldrawn but to say that process technology nodes are just a label without it being a measure of anything is a bit farther than I would go. SRAM cell size has decreased by approximately ~50% from generation to generation for as far back as I've been in the industry. The percentages bounce around from generation to generation, but the overall trend is for a 50% reduction. Decreasing SRAM cell size implies that the primary drawn features are getting ~30% smaller. And clearly if things are getting smaller on a consistent basis, then there is something measureable being reduced.

I think I know you well enough to know you don't mean to do it intentionally, but you've made a strawman argument there in that you are asserting that because successive nodes do deliver consistent improvements in their deliverables (sram density, etc) over past nodes and because surely there are physically measurable features within a given process technology (all of which is true, but I have not said any of this is untrue) that somehow this is to be invoked as proof that my assertion is untrue regarding node labels being simply labels.

I don't think it's a strawman arguement. Because the progress is consistent at each point, the labels have a deterministic measureable value, thus they are not meaningless labels, but notches on a measuring stick showing incremental progress over time. Changing the labels to meaningless numbers like "854, 856, 858" which have limited descriptive value, doesn't detract from the fact that these descriptors point to a measurable value on silicon. If you know where you started, and you know that SRAM area is reduced by ~50%, then you can determine with some level of accuracy what the size of a given size of memory is at each point.

I make the statement based on being right there in the decision rooms as new process technology nodes (something that already existed on paper as a label) had virtually every single physical and electrical attribute jockied around for yield/manufacturability reasons as well as risk to timeline and development cost. There is zero influence on these decisions stemming from the label given to the node.

Agreed.

We called the successor to the 45nm node as being the 32nm node for simple sake of the fact that is what marketing and media expected us to call the successor to our 45nm node. Had we used a different label then it would have appeared we were diverging from the rest of the industry.

Yes. Agreed that everything gets moved around and nothing gets scaled by a fixed amount - well, not since ~350nm. But, the end result is that certain devices - a latch, an SRAM cell - are basically 50% (+/- 10%) smaller than they were on the previous generation. And this is something specific and measureable. Even at Intel, where there are generic 854, 856 names to processes, a new name isn't given to a new process unless it shows a substantial, close-to-50%, size reduction for an SRAM cell over the previous process node. There are plenty of recipes at each process node - and device characteristics can change dramatically as the guys in Oregon tweak the recipe - but it doesn't get a new process node label unless the size of the SRAM area is ~50% smaller than it was at the last process label. I have seen substantially changes in electrical characteristics for a given process node from one iteration (called "revs") to the next, but it doesn't get a new process node label.

When a new node's specs are being "fleshed out" there is absolutely zero decision making going on to the tune of "well guys, this is going to be called the 32nm node so that means first and foremost we need 1/2 gate pitch to be 32nm" or "this is going to be called the 32nm node so that means first and foremost we need printed gate length, Ldrawn, to be 32nm".

Well, yes, but there are certain goals that need to be achieved in terms of device characteristics and one of these is that the main circuitry is smaller than before. ~50% smaller in terms of SRAM area. And SRAM now accounts for the largest portion of the higher end products and thus it's area has a substantial impact on yield. So while I agree that whatever is drawn can be whatever size you guys want it to be, the end result is ~50% smaller circuitry

There are design targets, i.e. deliverables, for a new node...50% areal reduction of some token circuit of merit (sram for some), 5x decrease in leakage, 20% increase in Idrive, etc. They are all based on successive iterative improvements from a pre-existing node or pre-existing specs for a node under development (N+1 vs N+2), etc.

There is a reason Intel internally refers to their 32nm node as the P1268 and 22nm as the P1270. Whether you call it 32nm or P1268, both descriptors are merely labels to differentiate the underlying process tech from prior and successive generations. And if I wanted to make false (and silly) maths with those labels to say silly stuff like ratios between them I could do things like say "CPU's on 22nm will be 22/32 = 69% the size of 32nm chips"...this is wronger than wrong, but no less correct than if I said "CPU's on P1270 will be P1268/P1270 = 99.8% the size of P1268 chips". In both cases I am treating a node label, a text item not a mathematical quantity, as if it were indeed a mathematical quantity which I can do maths with.

And this gets back to my point at the top - which is that you can, with a certain amount of error, do math with it.

Taking an arbitrary point in time, say, 180nm. For Intel, this process had a 5.59um^2 cell size. Now let's go foward 3 process nodes in time, 180->130->90->65nm. If you devide 5.59 by 2 three times, you get 0.7um^2 which is not too far off from the real value of 0.57um^2.

The basis on my thinking on the subject is pretty much slide 6 of this presentation:

The points along that line more or less line up with the extrapolated line, and the points on it are more or less equidistant. There's some error bars, but overall, it's a steady progression and if you know one point along it, you can extrapolate other points.

You making the argument that since things get smaller on a consistent basis (aka node reduction results in step-wise linear changes in deliverables) has nothing to do with what I am saying about the node label being nothing more than simply a label.

I'm saying that the label has some mathematical meaning at the macroscopic level - maybe just at Intel, which is the only process technology that I very familiar with. Not in terms of drawn values at the low levels which have lots of limitations due to OPC and phase-shifted masks and other things that I know little about, and not in terms of size of a CPU - because that's an arbitrary thing that is determined by the market as well as a lot of other variables - but in terms of the size of specific cells on the chip. Latches are problematic to use because it depends on whether it's a scan latch or not, whether it's a mulithreaded cell or not, whether it's a master-slave or a pulse latch, etc. But SRAM is used all over the chip, it's a good figure of merit for the size of a cache.

The gist of what you are saying - if I'm understanding correctly and you will no doubt correct me if I'm not - is that making a process recipe is a messy business and that all sorts of things get changed and none of these are determined by anything from the ITRS or anything else that you can measure with a 0.7X measuring stick consistently from one generation to the next. And I'm not debating that - you are far more of an expert in these matters than I am. But I am saying that there are goals to each process in terms of speed, and especially - at least at Intel - in terms of density and that these goals add up to a progression over time which has a concrete measureable and mathematical value.

#### Idontcare

##### Elite Member
Originally posted by: pm
And this gets back to my point at the top - which is that you can, with a certain amount of error, do math with it.

Taking an arbitrary point in time, say, 180nm. For Intel, this process had a 5.59um^2 cell size. Now let's go foward 3 process nodes in time, 180->130->90->65nm. If you devide 5.59 by 2 three times, you get 0.7um^2 which is not too far off from the real value of 0.57um^2.

The basis on my thinking on the subject is pretty much slide 6 of this presentation:

The points along that line more or less line up with the extrapolated line, and the points on it are more or less equidistant. There's some error bars, but overall, it's a steady progression and if you know one point along it, you can extrapolate other points.

What you are tracking there is the rate of change in the deliverables, the metrics of success, for each successive node. Again you really are just proving my point because look at what math you did...you counted the number of nodes (3 in your example) and applied an industry accepted expectation of the rate of change of the metrics (2x per node) to do your math. None of your math actually involves using the labels of the nodes themselves.

Let me do the following substitution - let's call 180nm as 1000au (arbitrary units), 130nm as 750au, 90nm can be called 562au, and 65nm can be relabeled as 421au.

Now let's see if changing node labels makes any difference to your example:

Taking an arbitrary point in time, say, 1000au. For Intel, this process had a 5.59um^2 cell size. Now let's go foward 3 process nodes in time, 1000->750->562->421. If you devide 5.59 by 2 three times, you get 0.7um^2 which is not too far off from the real value of 0.57um^2.

The points along that line more or less line up with the extrapolated line, and the points on it are more or less equidistant. There's some error bars, but overall, it's a steady progression and if you know one point along it, you can extrapolate other points.

The point is whether you call the node 1000au or 180nm or Grapefruit is irrelevant. You merely use the label to look at a look-up table to actually extract the relevant electrical and physical characteristics of that given process technology.

Intel's grapefruit node had an sram cellsize of 5.59um^2. Three nodes later, applying industry expectations of node entitlement, we would expect the sram cellsize to have shrunk to 0.70um^2. Whether Intel calls this third successor node the 65nm node or the Apple node is irrelevant to the maths employed in attempting to extrapolate the deliverables of the new node.

Telling you I own a 2005 Toyota Sienna doesn't tell you anything about when it was made, its HP, its mpg, or its resell value. But armed with the label of my asset you can then go and look up the various attributes of my minivan and compare its metrics to that of a 2004 model and 2006 model.

edit: forgot to add to the last sentence above: "And knowing the specifics of the 2004, 2005, and 2006 models of the Toyota Sienna still doesn't tell you jack about the specifics of the equivalent year models of Honda's Odyssey minivan...just as knowing specifics about Intel's 32nm node's deliverables tells you nothing about the deliverables for IBM's 32nm or Globalfoundries 32nm, etc".

As expected with labels, if Intel labeled their 32nm node the Apples node, and Globalfoundries labeled their 32nm node the Oranges node, and you proceeded to try and compare the two nodes in some one-dimensional metric of success analysis (such as Lg or Ldrawn) you would be rightly told you were comparing apples to oranges...just as you would be if you were comparing AMD's 32nm to Intel's 32nm (the labels themselves) versus comparing the metrics of success themselves (cell size of sram normalized to Vdd and clockspeed or some such).

#### pm

##### Elite Member Mobile Devices
Ok, I see what you are getting at. I still don't necessarily agree - it's like saying that numbers on a ruler aren't really numbers at all but labels for an arbitrary unit of measurement. Which I guess is true from a certain philosophical perspective, but that's a little bit deeper than I tend to think.

The ruler for me is the ~50% cell size reduction line - and the process node labels (I'll grant you, they are labels) are the notches along this ruler defined at fixed intervals. It is a self-fufilling prophecy, but it's still like a ruler. And you can do math by knowing the line and points because people made it that way, but there's still mathemtical value there.

I'm not sure that we are going to convince each other though - I've swung round to most your way of thinking, but at Intel at least, there's some mathematical value to the trend line and based on it I can make predictions about the future - at least within the next 9 years - and the predictions will be accurate (with some fudge for error).

#### Idontcare

##### Elite Member
Originally posted by: pm
Ok, I see what you are getting at. I still don't necessarily agree - it's like saying that numbers on a ruler aren't really numbers at all but labels for an arbitrary unit of measurement. Which I guess is true from a certain philosophical perspective, but that's a little bit deeper than I tend to think.

The ruler for me is the ~50% cell size reduction line - and the process node labels (I'll grant you, they are labels) are the notches along this ruler defined at fixed intervals. It is a self-fufilling prophecy, but it's still like a ruler. And you can do math by knowing the line and points because people made it that way, but there's still mathemtical value there.

I'm not sure that we are going to convince each other though - I've swung round to most your way of thinking, but at Intel at least, there's some mathematical value to the trend line and based on it I can make predictions about the future - at least within the next 9 years - and the predictions will be accurate (with some fudge for error).

I'm a bit confused...you appear to be arguing over whether or not the node label communicates information versus being meaningless...which is not the topic I thought we were talking about.

I am not arguing the label as being meaningless, nor am I arguing that the node label fails to communicate information.

But you have still yet to provide an example of what the node label itself does for you mathematically. How do you go from P1268 to 32nm to 0.149um^2 cellsize, or PMOS Idrive of 1.2nA/um or Vdd of 1.1V?

The node label of 32nm, as a mathematical entity being the arabic numeral thirty-two followed by the metric units of physical dimension nanometers, tells you nothing about anything relating to the process technology or the electrical characteristics of an IC fabricated with the process technology.

All your examples are "by association"...32nm is node N+1 from 45nm, so if you know a physical attribute of 45nm (a reference point) then you can extrapolate what it will likely be at N+1 (32nm) but not because the node itself is labeled 32nm versus 31nm or 33nm or Grapefruit or alpha tango but simply for the fact that it is "the next node, which means...".

As I said in the posts way above, it (the node label) serves the purpose of communicating that the process technology has iterated (same exact purpose served by associating auto models with a specific year) but you won't find anything under the hood that was 45nm in dimension at node N and 32nm at node N+1.

If I handed you a chip and told you nothing more than "it was fabricated with 22nm process technology" what would you be able to tell me about the chip? Physical dimensions of components or electrical characteristics of the device while in operation. Pretty much zilch. But if I handed you a chip and said "this chip was fabricated with node N+3, where for node N the sram cellsize was 1um^2 and Lg was 40nm"...now what would you tell me about the chip I just handed you? (you'd use expectations called "node entitlement" to reason that after three successive node shrinks the cellsize was now 0.125um^2 and the Lg was around 14nm.

There really isn't anything deeply philosophical about this, its not about questioning the meaning of the iterations on the ruler nor the units, it's about whether or not the label applied is a text label or truly mathematical descriptor of some physical attribute of the process technology.

What physical component in Intel's 45nm process node is intentionally 45nm (within process variation) that was intentionally 65nm in their 65nm node and will be 32nm in their 32nm node? If your answer is "nothing" then you have fully acknowledged it is simply a label, a label that iterates and communicates information based on node-iteration expectations but a label nonetheless that has little to do with specific physical dimensions (despite the label itself being a physical dimension at face value).

I'll give you another real-world example - clockspeed versus performance ratings. You know exactly what the clockspeed is for a 3.2GHz Pentium 4...it's 3.2GHz plus or minus a little based on spread-spectrum settings. This is an example where the product labeling (3.2GHz Pentium 4) also means something mathematical and real (the cpu's clockspeed really is 3.2GHz).

But what does an "Athlon 64 3200+" tell you about the underlying chip's operational characteristics? Does the Athlon 64 operate at 3200+ clockspeed? Nope, it's just a label. Is 3200+ intended to be an incremental scaling that communicates to the user it is faster than a 3000+ chip but slower than a 3400+ chip? You bet it does, but doesn't change the fact the 3000+ and 3400+ chips aren't operating at 3000+ and 3400+ clockspeeds. But the performance rating communicates information nonetheless.

It's the same way with node labels, although perhaps a little less valuable because they communicate nothing about the attributes of the node itself other than we know where those attributes should fall in reference to prior nodes and successive nodes.

#### taltamir

##### Lifer
thanks for the info.

Idontcare, do you know what is the width of the smallest structure manufactured in current / future node tech? that will give me something to do math with.

#### Idontcare

##### Elite Member
Originally posted by: taltamir
thanks for the info.

Idontcare, do you know what is the width of the smallest structure manufactured in current / future node tech? that will give me something to do math with.

The gate oxide is the "smallest" dimensional component of current and future nodes. It is the dielectric insulator layer that separates the voltage/current applied to the gate (residing above the gate oxide in planar mosfets) from the drain and the source.

Gate Oxide Leakage Current Analysis and Reduction for VLSI Circuits

For plasma-nitrided gate oxides (SiON) the gate oxide is on the order of 10-14Å. It is not physically measurable, instead the physical thickness of the gate oxide is inferred by way of electrical measurements being correlated to extrapolated values from known physical thickness results.

Modeling of the gate leakage current reduction in MOSFET with ultra-thin nitrided gate oxide

The EOT (equivalent oxide thickness, also sometimes referred to as the effective oxide thickness) applies to both modern plasma-nitrided gate oxides as well as high-gate gate oxides such as the kind Intel uses in their 45nm node.

See page 3 of Technology backgrounder: High-k gate oxides for a nice and easy going conversation on EOT.

So what is the physically thinnest gate oxide in production or slated to ever go into production? Around ~9Å, or 4-5 atoms thick, although the leakage is dreadfully high at that point.

See Fig 2 of Gate Oxide Leakage and Delay Tradeoffs for Dual Tox Circuits and note the scale of the y-axis is a log scale.

#### Markfw

##### Moderator Emeritus, Elite Member
Dudes, not really complaining (will not move thread), but shouldn't this be in the "highly technical" forum ?

#### TuxDave

##### Lifer
Originally posted by: Idontcare

...

I am not arguing the label as being meaningless, nor am I arguing that the node label fails to communicate information.

...

The node label of 32nm, as a mathematical entity being the arabic numeral thirty-two followed by the metric units of physical dimension nanometers, tells you nothing about anything relating to the process technology or the electrical characteristics of an IC fabricated with the process technology.

...

It's the same way with node labels, although perhaps a little less valuable because they communicate nothing about the attributes of the node itself other than we know where those attributes should fall in reference to prior nodes and successive nodes.

Sorry if I overcropped your paragraph but there's too many points to address. Agreed the node label doesn't tell us ENOUGH information about the process but it does give us a measurable physical characteristic of the design or design process. There are mathematical equations on the electrical characteristic properties of the process that can use the node label as one of its variables. I'm not really sure what point you are trying to argue. It's like saying your speed is just a label and not physical because with the speed alone you cannot figure out how far you can go. Maybe I'm reading your post wrong but yeah it doesn't tell you everything about the process but why would that make it any less physical and measurable?

#### Idontcare

##### Elite Member
Originally posted by: TuxDave
There are mathematical equations on the electrical characteristic properties of the process that can use the node label as one of its variables.

That's an empirical correlation, yes, no doubt with the cause and effect entirely reversed.

As I mentioned above, associating metric XYZ (Lgmin, Ldrawn, Idrive, cellsize, etc) with the node label is to be expected, but you don't need the label to be numeric in order for this association to hold true.

Nor does it follow that metric XYZ exists because the node label is some specific value.

Your 45nm technology node's sram cellsize has nothing to do with the physical measurement 45nm, nor does your node's NMOS Idrive, or IDsat, or gate pitch, or M1 pitch. The node label "45nm" is intended to communicate that all these metrics have been iterated from those observed in "65nm" but the cause and effect of the node label is entirely missing. It's carried on for purely legacy reasons and marketing acceptance.

Whether Intel refers to their next production node as 32nm or P1268 has zero bearing on the actual physical measurements of the features contained in devices manufactured on that technology.

Originally posted by: TuxDave
I'm not really sure what point you are trying to argue.

I was explaining to the OP the reality of being misled by presuming the node label represents a physical measurement of something in the underlying process technology:

Originally posted by: Idontcare
Also your dimensionality will be off if you equate the node label (40nm, 32nm, etc) with the physical dimensions of an underlying component such as the channel length (Lg) as you have in your OP. For 40nm the smallest Lg will be ~20-22nm and for 32nm the Lg will be around ~16-18nm (it varies by company of course).

Originally posted by: TuxDave
Maybe I'm reading your post wrong but yeah it doesn't tell you everything about the process but why would that make it any less physical and measurable?

It doesn't tell you anything about the underlying process, unless you establish a pre-existing correlation table between the label and some property you can measure. But that is to be expected of a label, all that is intended to be conveyed is a unique identifier with which you can go lookup the actual physical/electrical info if you like.

I'll ask you the same question posed to pm above:

Originally posted by: Idontcare
What physical component in Intel's 45nm process node is intentionally 45nm (within process variation) that was intentionally 65nm in their 65nm node and will be 32nm in their 32nm node?

Here is another Socratic method styled question - you know GlobalFoundries is going to debut a "32nm" node...given this information (node is labeled 32nm) can you tell me anything specific about the physical dimensions of any design rules for GF's 32nm node? What about 22nm? And 16nm?

#### TuxDave

##### Lifer
Originally posted by: Idontcare

Your 45nm technology node's sram cellsize has nothing to do with the physical measurement 45nm, nor does your node's NMOS Idrive, or IDsat, or gate pitch, or M1 pitch. The node label "45nm" is intended to communicate that all these metrics have been iterated from those observed in "65nm" but the cause and effect of the node label is entirely missing. It's carried on for purely legacy reasons and marketing acceptance.

Whether Intel refers to their next production node as 32nm or P1268 has zero bearing on the actual physical measurements of the features contained in devices manufactured on that technology.

It doesn't tell you anything about the underlying process, unless you establish a pre-existing correlation table between the label and some property you can measure. But that is to be expected of a label, all that is intended to be conveyed is a unique identifier with which you can go lookup the actual physical/electrical info if you like.

I've been a little out of the fabrication business but if you build a DRAM on a 45nm process and you manage to get a very precise ruler, what is the physical gate length at the top of the metal gate? (furthest away from the silicon) I expected that to be 45nm. The effective gate length is then the 45nm minus diffusion length and etch rate and whatever else you have.

On the design side, on a 45nm process we see 45nm drawn features and so if there's some wacko optical translation from our design to a process mask (which there definitely are) I can't really account for that.

Idrive IDsat is impossible to tell with even the physical effective gate length because it's a function of dopant concentration and temperature and effective gate length (which I argue is a function of drawn gate length or process node).

dp

#### Idontcare

##### Elite Member
Originally posted by: TuxDave
Originally posted by: Idontcare

Your 45nm technology node's sram cellsize has nothing to do with the physical measurement 45nm, nor does your node's NMOS Idrive, or IDsat, or gate pitch, or M1 pitch. The node label "45nm" is intended to communicate that all these metrics have been iterated from those observed in "65nm" but the cause and effect of the node label is entirely missing. It's carried on for purely legacy reasons and marketing acceptance.

Whether Intel refers to their next production node as 32nm or P1268 has zero bearing on the actual physical measurements of the features contained in devices manufactured on that technology.

It doesn't tell you anything about the underlying process, unless you establish a pre-existing correlation table between the label and some property you can measure. But that is to be expected of a label, all that is intended to be conveyed is a unique identifier with which you can go lookup the actual physical/electrical info if you like.

I've been a little out of the fabrication business but if you build a DRAM on a 45nm process and you manage to get a very precise ruler, what is the physical gate length at the top of the metal gate? (furthest away from the silicon) I expected that to be 45nm. The effective gate length is then the 45nm minus diffusion length and etch rate and whatever else you have.

On the design side, on a 45nm process we see 45nm drawn features and so if there's some wacko optical translation from our design to a process mask (which there definitely are) I can't really account for that.

Idrive IDsat is impossible to tell with even the physical effective gate length because it's a function of dopant concentration and temperature and effective gate length (which I argue is a function of drawn gate length or process node).

Intel no doubt has a corporate license for Chipworks and Semiconductor Insights, I think you would do yourself a big favor to pull up a few of the latest cross-section publications relating to dram as well as the one's done on Intel's 45nm penryn and bloomfield. This sub-topic has definitely gone beyond the point of becoming pointless in its own sake for further discussion IMHO. I've ran out of examples and am at the stage where I can't fathom a method or approach to spell out the reality of node labels any more simply or plainly.

#### TuxDave

##### Lifer
Originally posted by: Idontcare

Intel no doubt has a corporate license for Chipworks and Semiconductor Insights, I think you would do yourself a big favor to pull up a few of the latest cross-section publications relating to dram as well as the one's done on Intel's 45nm penryn and bloomfield. This sub-topic has definitely gone beyond the point of becoming pointless in its own sake for further discussion IMHO. I've ran out of examples and am at the stage where I can't fathom a method or approach to spell out the reality of node labels any more simply or plainly.

Thanks for the pointer of the publication and it's too bad you don't want to continue this discussion. It's pretty easy to convince me with a concrete example but as far as I know, given Penryn's 45nm process:

http://www.semiconductorblog.c...nryn_transistor-04.JPG

The top of that white rectangle (including the black rectangle in the middle which I'm assuming is the gate contact) is 45nm. If you have a document that you know of it'll probably save me some time of poking around.

#### Idontcare

##### Elite Member
Originally posted by: TuxDave
Originally posted by: Idontcare

Intel no doubt has a corporate license for Chipworks and Semiconductor Insights, I think you would do yourself a big favor to pull up a few of the latest cross-section publications relating to dram as well as the one's done on Intel's 45nm penryn and bloomfield. This sub-topic has definitely gone beyond the point of becoming pointless in its own sake for further discussion IMHO. I've ran out of examples and am at the stage where I can't fathom a method or approach to spell out the reality of node labels any more simply or plainly.

Thanks for the pointer of the publication and it's too bad you don't want to continue this discussion. It's pretty easy to convince me with a concrete example but as far as I know, given Penryn's 45nm process:

http://www.semiconductorblog.c...nryn_transistor-04.JPG

The top of that white rectangle (including the black rectangle in the middle which I'm assuming is the gate contact) is 45nm. If you have a document that you know of it'll probably save me some time of poking around.

TuxDave how can I provide you concrete proof of the lack of the existence of something?

All I can do to prove this to you is continue to ask you to provide proof that the node label is more than just a label, because I assure you if you scratch the surface on the preconceptions you have about it you will be in for surprise.

I don't know what I am supposed to gather from the cross-section sem you provide. Are you trying to prove to me that there are things that measure out to be 45nm in dimension when produced on Intel's 45nm process technology? Look around enough and you'll find things larger and things even smaller, but coincidental design of a feature size to that of the node label is just that, coincidental.

Or are you arguing that Intel specifically restricted the design size of that specific feature to be exactly equal to the node label? Does that same feature you highlight in the 45nm xsem measure out to be 65nm in a 65nm based processor and will be 32nm in a 32nm based processor? Do you believe that same feature is also 45nm on AMD's 45nm processors?

Originally posted by: TuxDave
The top of that white rectangle (including the black rectangle in the middle which I'm assuming is the gate contact) is 45nm. If you have a document that you know of it'll probably save me some time of poking around.

FWIW that white rectangle is the gate, and now you can't really convince me that you believe the minimum gate length of Intel's 45nm node is 45nm...you got to go back to 90nm Prescott xsems to find min Lg's of that dimension.

#### TuxDave

##### Lifer
Originally posted by: Idontcare
Or are you arguing that Intel specifically restricted the design size of that specific feature to be exactly equal to the node label? Does that same feature you highlight in the 45nm xsem measure out to be 65nm in a 65nm based processor and will be 32nm in a 32nm based processor? Do you believe that same feature is also 45nm on AMD's 45nm processors?

Yes. And it's not so much restricted but more like that was their design goal to get that one feature to the node label's physical length

#### TuxDave

##### Lifer
Originally posted by: Idontcare
Originally posted by: TuxDave
The top of that white rectangle (including the black rectangle in the middle which I'm assuming is the gate contact) is 45nm. If you have a document that you know of it'll probably save me some time of poking around.

FWIW that white rectangle is the gate, and now you can't really convince me that you believe the minimum gate length of Intel's 45nm node is 45nm...you got to go back to 90nm Prescott xsems to find min Lg's of that dimension.

Not at the top of the gate where it's the drawn gate length. At the bottom minus the diffusion length sure the 90nm process may have had a 45nm effective gate length and thus the 45nm process has an effective gate length of something smaller. That's why I specified the top of the gate. And if you look at the scale at the bottom and do some handwaving, it looks to be about right.

Edit And the ITRS statement isn't saying that "process node is becoming an arbitrary label without any relation to the process" but more of a "process node isn't good enough to describe the scaling of technology".

#### SunSamurai

##### Diamond Member
bond length == lattice constant?